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Bump DiffTest for refactor SimTop #238

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Bump DiffTest for refactor SimTop #238

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2 changes: 1 addition & 1 deletion difftest
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Submodule difftest updated 4 files
+3 −80 src/main/scala/Difftest.scala
+101 −0 src/main/scala/SimTop.scala
+7 −6 src/test/scala/DifftestTop.scala
+2 −2 src/test/vsrc/vcs/top.v
11 changes: 8 additions & 3 deletions src/main/scala/sim/NutShellSim.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ import difftest._
import nutcore.NutCoreConfig
import system._

class SimTop extends Module {
class NutShellSim extends Module with HasDiffTestInterfaces {
lazy val config = NutCoreConfig(FPGAPlatform = false)
val soc = Module(new NutShell()(config))
val mem = Module(new AXI4RAM(memByte = 2L * 1024 * 1024 * 1024, useBlackBox = true))
Expand All @@ -41,6 +41,11 @@ class SimTop extends Module {

soc.io.meip := mmio.io.meip

val difftest = DifftestModule.finish("nutshell")
difftest.uart <> mmio.io.uart
override def cpuName: Option[String] = Some("NutShell")

val uart = IO(new UARTIO)
uart <> mmio.io.uart
override def connectTopIOs(difftest: DifftestTopIO): Unit = {
difftest.uart <> uart
}
}
18 changes: 10 additions & 8 deletions src/test/scala/TopMain.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -20,9 +20,9 @@ import chisel3._
import chisel3.stage.ChiselGeneratorAnnotation
import circt.stage._
import device.AXI4VGA
import difftest.DifftestModule
import difftest.{DifftestModule, DifftestTopIO, HasDiffTestInterfaces}
import nutcore.NutCoreConfig
import sim.SimTop
import sim.NutShellSim
import system.NutShell

class Top extends Module {
Expand All @@ -36,15 +36,17 @@ class Top extends Module {
dontTouch(vga.io)
}

class FpgaDiffTop extends Module {
override lazy val desiredName: String = "SimTop"
class FpgaDiffTop extends Module with HasDiffTestInterfaces {
lazy val config = NutCoreConfig(FPGADifftest = true)
val soc = Module(new NutShell()(config))
val io = IO(soc.io.cloneType)
soc.io <> io

val difftest = DifftestModule.finish("nutshell")
dontTouch(soc.io)
override def cpuName: Option[String] = Some("NutShell")
override def connectTopIOs(difftest: DifftestTopIO): Unit = {
val io = IO(chiselTypeOf(this.io))
io <> this.io
}
}

object TopMain extends App {
Expand Down Expand Up @@ -79,9 +81,9 @@ object TopMain extends App {
}

val generator = if (board == "sim") {
ChiselGeneratorAnnotation(() => new SimTop)
ChiselGeneratorAnnotation(() => DifftestModule.top(new NutShellSim))
} else if (board == "fpgadiff") {
ChiselGeneratorAnnotation(() => new FpgaDiffTop)
ChiselGeneratorAnnotation(() => DifftestModule.top(new FpgaDiffTop))
}
else {
ChiselGeneratorAnnotation(() => new Top)
Expand Down