Skip to content

Bump Chisel 7.0.0 #235

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Sep 19, 2025
Merged

Bump Chisel 7.0.0 #235

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions build.sc
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,8 @@ import coursier.maven.MavenRepository

object ivys {
val scala = "2.13.14"
val chisel = ivy"org.chipsalliance::chisel:6.7.0"
val chiselPlugin = ivy"org.chipsalliance:::chisel-plugin:6.7.0"
val chisel = ivy"org.chipsalliance::chisel:7.0.0"
val chiselPlugin = ivy"org.chipsalliance:::chisel-plugin:7.0.0"
}

trait CommonModule extends ScalaModule {
Expand Down
2 changes: 1 addition & 1 deletion difftest
Open in desktop
Submodule difftest updated 31 files
+18 −2 .github/workflows/nightly.yml
+10 −1 Makefile
+1 −1 README.md
+1 −1 build.sc
+43 −18 src/main/scala/Batch.scala
+4 −1 src/main/scala/Bundles.scala
+0 −1 src/main/scala/Coverage.scala
+12 −3 src/main/scala/Difftest.scala
+1 −10 src/main/scala/Gateway.scala
+23 −11 src/main/scala/Preprocess.scala
+19 −13 src/main/scala/Squash.scala
+1 −1 src/main/scala/common/WiringControl.scala
+1 −1 src/main/scala/util/Query.scala
+0 −248 src/main/scala/util/VerificationExtractor.scala
+3 −7 src/test/csrc/difftest/difftest.cpp
+1 −0 src/test/csrc/fpga/serial_port.cpp
+45 −0 src/test/csrc/plugin/simfrontend/debug.h
+588 −0 src/test/csrc/plugin/simfrontend/ftq.cpp
+229 −0 src/test/csrc/plugin/simfrontend/ftq.h
+220 −0 src/test/csrc/plugin/simfrontend/simfrontend.cpp
+33 −0 src/test/csrc/plugin/simfrontend/simfrontend.h
+134 −0 src/test/csrc/plugin/simfrontend/tracereader.cpp
+58 −0 src/test/csrc/plugin/simfrontend/tracereader.h
+12 −0 src/test/csrc/verilator/emu.cpp
+1 −0 src/test/csrc/verilator/emu.h
+38 −11 src/test/vsrc/fpga/Difftest2AXI.v
+52 −0 src/test/vsrc/fpga/bram_port.v
+56 −0 src/test/vsrc/fpga/dual_buffer_bram.sv
+31 −0 src/test/vsrc/fpga/fpga_clock_gate.v
+9 −2 src/test/vsrc/fpga_sim/xdma_clock.v
+2 −2 src/test/vsrc/fpga_sim/xdma_wrapper.v
3 changes: 2 additions & 1 deletion src/main/scala/system/NutShell.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -78,7 +78,8 @@ class NutShell(implicit val p: NutCoreConfig) extends Module with HasSoCParamete
l2cacheIn
} else xbar.io.out
val l2Empty = Wire(Bool())
l2cacheOut <> Cache(in = l2cacheIn, mmio = 0.U.asTypeOf(new SimpleBusUC) :: Nil, flush = "b00".U, empty = l2Empty, enable = true)(
val mmio = WireInit(0.U.asTypeOf(new SimpleBusUC))
l2cacheOut <> Cache(in = l2cacheIn, mmio = mmio :: Nil, flush = "b00".U, empty = l2Empty, enable = true)(
CacheConfig(name = "l2cache", totalSize = 128, cacheLevel = 2))
l2cacheOut.coh.resp.ready := true.B
l2cacheOut.coh.req.valid := false.B
Expand Down