Merge pull request #43 from chenguokai/master

AugustusWillisWang · web-flow · commit 104082fd5498 · 2020-11-30T21:08:19.000+08:00
Simplebus: simplify debug condition
diff --git a/src/main/scala/bus/simplebus/Crossbar.scala b/src/main/scala/bus/simplebus/Crossbar.scala
@@ -40,7 +40,7 @@ class SimpleBusCrossbar1toN(addressSpace: List[(Long, Long)]) extends Module {
   val outSelResp = io.out(outSelIdxResp)
   val reqInvalidAddr = io.in.req.valid && !outSelVec.asUInt.orR
 
-  when(!(!io.in.req.valid || outSelVec.asUInt.orR) || !(!(io.in.req.valid && outSelVec.asUInt.andR))){
+  when((io.in.req.valid && !outSelVec.asUInt.orR) || (io.in.req.valid && outSelVec.asUInt.andR)){
     Debug(){
       printf("crossbar access bad addr %x, time %d\n", addr, GTimer())
     }

Original file line number	Diff line number	Diff line change
`@@ -40,7 +40,7 @@ class SimpleBusCrossbar1toN(addressSpace: List[(Long, Long)]) extends Module {`
`40`	`40`	`val outSelResp = io.out(outSelIdxResp)`
`41`	`41`	`val reqInvalidAddr = io.in.req.valid && !outSelVec.asUInt.orR`
`42`	`42`
`43`		`- when(!(!io.in.req.valid \|\| outSelVec.asUInt.orR) \|\| !(!(io.in.req.valid && outSelVec.asUInt.andR))){`
	`43`	`+ when((io.in.req.valid && !outSelVec.asUInt.orR) \|\| (io.in.req.valid && outSelVec.asUInt.andR)){`
`44`	`44`	`Debug(){`
`45`	`45`	`printf("crossbar access bad addr %x, time %d\n", addr, GTimer())`
`46`	`46`	`}`