Add support for Rockchip rk3588

core/arch/arm/plat-rockchip/conf.mk

@@ -56,6 +56,24 @@ CFG_SHMEM_SIZE   ?= 0x00400000
 CFG_EARLY_CONSOLE ?= n
 endif
 
+ifeq ($(PLATFORM_FLAVOR),rk3588)
+include core/arch/arm/cpu/cortex-armv8-0.mk
+$(call force,CFG_TEE_CORE_NB_CORE,8)  # Number of cores in the platform
+$(call force,CFG_ARM_GICV3,y)
+$(call force,CFG_CRYPTO_WITH_CE,y)
+
+CFG_TZDRAM_START ?= 0x08400000
+CFG_TZDRAM_SIZE ?= 0x02000000
+CFG_SHMEM_START ?= 0x0a4000000
+CFG_SHMEM_SIZE ?= 0x00400000
+
+CFG_EARLY_CONSOLE ?= y
+CFG_EARLY_CONSOLE_BASE ?= UART2_BASE
+CFG_EARLY_CONSOLE_SIZE ?= UART2_SIZE
+CFG_EARLY_CONSOLE_BAUDRATE ?= 1500000
+CFG_EARLY_CONSOLE_CLK_IN_HZ ?= 24000000
+endif
+
 ifeq ($(platform-flavor-armv8),1)
 $(call force,CFG_ARM64_core,y)
 $(call force,CFG_WITH_ARM_TRUSTED_FW,y)

core/arch/arm/plat-rockchip/platform_config.h

@@ -1,7 +1,8 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
+/* SPDX-License-Identifier: BSD-3-Clause */
 /*
  * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd.
  * Copyright (C) 2019, Theobroma Systems Design und Consulting GmbH
+ * Copyright (c) 2024, Rockchip, Inc. All rights reserved.
  */
 
 #ifndef PLATFORM_CONFIG_H
@@ -85,6 +86,35 @@
 #define FIREWALL_DDR_BASE	0xff534000
 #define FIREWALL_DDR_SIZE	SIZE_K(16)
 
+#elif defined(PLATFORM_FLAVOR_rk3588)
+
+#define GIC_BASE		0xfe600000
+#define GIC_SIZE		SIZE_K(64)
+#define GICC_BASE		0
+#define GICD_BASE		GIC_BASE
+#define GICR_BASE		(GIC_BASE + 0x80000)
+
+#define UART0_BASE		0xfd890000
+#define UART0_SIZE		SIZE_K(64)
+
+#define UART1_BASE		0xfeb40000
+#define UART1_SIZE		SIZE_K(64)
+
+#define UART2_BASE		0xfeb50000
+#define UART2_SIZE		SIZE_K(64)
+
+#define UART3_BASE		0xfeb60000
+#define UART3_SIZE		SIZE_K(64)
+
+#define SGRF_BASE		0xfd58c000
+#define SGRF_SIZE		SIZE_K(64)
+
+#define FIREWALL_DDR_BASE	0xfe030000
+#define FIREWALL_DDR_SIZE	SIZE_K(32)
+
+#define FIREWALL_DSU_BASE	0xfe010000
+#define FIREWALL_DSU_SIZE	SIZE_K(32)
+
 #else
 #error "Unknown platform flavor"
 #endif

core/arch/arm/plat-rockchip/platform_rk3588.c

@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (C) 2019, Theobroma Systems Design und Consulting GmbH
+ * Copyright (c) 2024, Rockchip, Inc. All rights reserved.
+ *
+ */
+
+#include <common.h>
+#include <io.h>
+#include <kernel/panic.h>
+#include <mm/core_memprot.h>
+#include <platform.h>
+#include <platform_config.h>
+
+#define FIREWALL_DDR_RGN(i)             ((i) * 0x4)
+#define FIREWALL_DDR_CON                0xf0
+#define FIREWALL_DSU_RGN(i)             ((i) * 0x4)
+#define FIREWALL_DSU_CON(i)             (0xf0 + ((i) * 0x4))
+
+#define RG_MAP_SECURE(top, base)        \
+        (((((top) - 1) & 0x7fff) << 16) | ((base) & 0x7fff))
+
+#define DDR_CHN_CNT                     4
+
+register_phys_mem_pgdir(MEM_AREA_IO_SEC, FIREWALL_DDR_BASE, FIREWALL_DDR_SIZE);
+register_phys_mem_pgdir(MEM_AREA_IO_SEC, FIREWALL_DSU_BASE, FIREWALL_DSU_SIZE);
+
+int platform_secure_ddr_region(int rgn, paddr_t st, size_t sz)
+{
+	vaddr_t fw_ddr_base = (vaddr_t)phys_to_virt_io(FIREWALL_DDR_BASE, FIREWALL_DDR_SIZE);
+	vaddr_t fw_dsu_base = (vaddr_t)phys_to_virt_io(FIREWALL_DSU_BASE, FIREWALL_DSU_SIZE);
+	paddr_t ed = st + sz;
+	uint32_t st_mb = st / SIZE_M(1);
+	uint32_t ed_mb = ed / SIZE_M(1);
+	uint32_t i;
+
+	if (!fw_ddr_base || !fw_dsu_base)
+		panic();
+
+	assert(rgn <= 7);
+	assert(st < ed);
+
+	/* Check aligned 1MB */
+	assert(st % SIZE_M(1) == 0);
+	assert(ed % SIZE_M(1) == 0);
+
+	DMSG("protecting region %d: 0x%lx-0x%lx", rgn, st, ed);
+
+	/* Map secure region in DDR */
+	io_write32(fw_ddr_base + FIREWALL_DDR_RGN(rgn), RG_MAP_SECURE(ed_mb, st_mb));
+
+	/* Map secure region in each DSU channel and enable */
+	for (i = 0; i < DDR_CHN_CNT; i++) {
+		io_write32(fw_dsu_base + FIREWALL_DSU_RGN(i), RG_MAP_SECURE(ed_mb, st_mb));
+		io_setbits32(fw_dsu_base + FIREWALL_DSU_CON(i), BIT(rgn));
+	}
+
+	/* Enable secure region for DDR */
+	io_setbits32(fw_ddr_base + FIREWALL_DDR_CON, BIT(rgn));
+
+	return 0;
+}

core/arch/arm/plat-rockchip/sub.mk

@@ -4,6 +4,7 @@ srcs-y += platform.c
 srcs-$(PLATFORM_FLAVOR_px30) += platform_px30.c
 srcs-$(PLATFORM_FLAVOR_rk322x) += platform_rk322x.c
 srcs-$(PLATFORM_FLAVOR_rk3399) += platform_rk3399.c
+srcs-$(PLATFORM_FLAVOR_rk3588) += platform_rk3588.c
 
 ifeq ($(PLATFORM_FLAVOR),rk322x)
 srcs-y += plat_init.S