LEAP Frontend

LEAP (Logic nEtwork-Aware Pipelining) is a framework for exploiting logic synthesis and technology mapping to improve the performance of high-level synthesis (HLS) tools. LEAP is implemented in Python and is open-source under the MIT license.

Read the full documentation.

Why LEAP?

For better HLS performance. Conventional synthesis flows apply high-level synthesis (HLS) before logic synthesis and technology mapping, where the majority of circuit's structural and functional information are determined. Lacking these informtion, HLS algorithms such as pipelining often make suboptimal decisions that are not revertable by subsequent synthesis stages. LEAP addresses this issue by integrating logic synthesis and technology mapping into HLS, enabling HLS algorithms to make better decisions based on the circuit's structural and functional information.

What LEAP-frontend does?

LEAP frontend:

• Takes the behavioral description of a circuit in Verilog as input.
• Transforms the behavioral description into a graph
• Apply customized lossless algorithms on the graph
• Write the graph into different formats for further processing in the backend

Getting Started

Install LEAP-frontend using pip:

pip install leap_frontend

Usage

In Python, you can use LEAP-frontend as follows:

from frontend import *

if __name__ == "__main__":
    netlist: Netlist = readVerilog("examples/verilogs/demo/simple.v")
    dot = exportDOT(netlist.getModuleAt(0))
    dot.write("output.dot")
    writeVerilog(netlist, "output.v")