Revert "[wasm][revec] Enable simd256 and revec for Pmin/Pmax op"

This reverts commit c40596b.

Reason for revert:
https://ci.chromium.org/ui/p/v8/builders/ci/V8%20Linux64/53401/overview
This might requires some test skips for the noavx cases.

Original change's description:
> [wasm][revec] Enable simd256 and revec for Pmin/Pmax op
>
> Bug: v8:12716
> Change-Id: Ifdb9e02f72acc2b1b9f11fd1f268e03f90fcf1f7
> Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4626192
> Reviewed-by: Thibaud Michaud <thibaudm@chromium.org>
> Commit-Queue: Yuheng Wei <yuheng.wei@intel.com>
> Cr-Commit-Position: refs/heads/main@{#88552}

Bug: v8:12716
Change-Id: I44fb0748ad787bb4f1504ef5fd8496b34d7cfb6e
No-Presubmit: true
No-Tree-Checks: true
No-Try: true
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/4650760
Auto-Submit: Michael Achenbach <machenbach@chromium.org>
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Owners-Override: Michael Achenbach <machenbach@chromium.org>
Commit-Queue: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Cr-Commit-Position: refs/heads/main@{#88557}

src/compiler/backend/instruction-selector.cc

@@ -4310,14 +4310,6 @@ void InstructionSelectorT<TurbofanAdapter>::VisitNode(Node* node) {
       return MarkAsSimd256(node), VisitI16x16ExtAddPairwiseI8x32S(node);
     case IrOpcode::kI16x16ExtAddPairwiseI8x32U:
       return MarkAsSimd256(node), VisitI16x16ExtAddPairwiseI8x32U(node);
-    case IrOpcode::kF32x8Pmin:
-      return MarkAsSimd256(node), VisitF32x8Pmin(node);
-    case IrOpcode::kF32x8Pmax:
-      return MarkAsSimd256(node), VisitF32x8Pmax(node);
-    case IrOpcode::kF64x4Pmin:
-      return MarkAsSimd256(node), VisitF64x4Pmin(node);
-    case IrOpcode::kF64x4Pmax:
-      return MarkAsSimd256(node), VisitF64x4Pmax(node);
 #endif  //  V8_TARGET_ARCH_X64
     default:
       FATAL("Unexpected operator #%d:%s @ node #%d", node->opcode(),

src/compiler/backend/x64/code-generator-x64.cc

@@ -3654,30 +3654,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       ASSEMBLE_SIMD_BINOP(maxps);
       break;
     }
-    case kX64F32x8Pmin: {
-      YMMRegister dst = i.OutputSimd256Register();
-      CpuFeatureScope avx_scope(masm(), AVX);
-      __ vminps(dst, i.InputSimd256Register(0), i.InputSimd256Register(1));
-      break;
-    }
-    case kX64F32x8Pmax: {
-      YMMRegister dst = i.OutputSimd256Register();
-      CpuFeatureScope avx_scope(masm(), AVX);
-      __ vmaxps(dst, i.InputSimd256Register(0), i.InputSimd256Register(1));
-      break;
-    }
-    case kX64F64x4Pmin: {
-      YMMRegister dst = i.OutputSimd256Register();
-      CpuFeatureScope avx_scope(masm(), AVX);
-      __ vminpd(dst, i.InputSimd256Register(0), i.InputSimd256Register(1));
-      break;
-    }
-    case kX64F64x4Pmax: {
-      YMMRegister dst = i.OutputSimd256Register();
-      CpuFeatureScope avx_scope(masm(), AVX);
-      __ vmaxpd(dst, i.InputSimd256Register(0), i.InputSimd256Register(1));
-      break;
-    }
     case kX64F32x4Round: {
       RoundingMode const mode =
           static_cast<RoundingMode>(MiscField::decode(instr->opcode()));

src/compiler/backend/x64/instruction-codes-x64.h

@@ -360,11 +360,7 @@ namespace compiler {
   V(X64I32x8ExtMulI16x8U)                            \
   V(X64I16x16ExtMulI8x16S)                           \
   V(X64I16x16ExtMulI8x16U)                           \
-  V(X64TraceInstruction)                             \
-  V(X64F32x8Pmin)                                    \
-  V(X64F32x8Pmax)                                    \
-  V(X64F64x4Pmin)                                    \
-  V(X64F64x4Pmax)
+  V(X64TraceInstruction)
 // Addressing modes represent the "shape" of inputs to an instruction.
 // Many instructions support multiple addressing modes. Addressing modes
 // are encoded into the InstructionCode of the instruction and tell the

src/compiler/backend/x64/instruction-scheduler-x64.cc

@@ -154,10 +154,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kX64F64x2Qfms:
     case kX64Minpd:
     case kX64Maxpd:
-    case kX64F32x8Pmin:
-    case kX64F32x8Pmax:
-    case kX64F64x4Pmin:
-    case kX64F64x4Pmax:
     case kX64F64x2Round:
     case kX64F64x2ConvertLowI32x4S:
     case kX64F64x4ConvertI32x4S:

src/compiler/backend/x64/instruction-selector-x64.cc

@@ -4981,26 +4981,6 @@ void InstructionSelectorT<Adapter>::VisitF64x2Pmax(Node* node) {
   VisitMinOrMax(this, node, kX64Maxpd, true);
 }
 
-template <typename Adapter>
-void InstructionSelectorT<Adapter>::VisitF32x8Pmin(Node* node) {
-  VisitMinOrMax(this, node, kX64F32x8Pmin, true);
-}
-
-template <typename Adapter>
-void InstructionSelectorT<Adapter>::VisitF32x8Pmax(Node* node) {
-  VisitMinOrMax(this, node, kX64F32x8Pmax, true);
-}
-
-template <typename Adapter>
-void InstructionSelectorT<Adapter>::VisitF64x4Pmin(Node* node) {
-  VisitMinOrMax(this, node, kX64F64x4Pmin, true);
-}
-
-template <typename Adapter>
-void InstructionSelectorT<Adapter>::VisitF64x4Pmax(Node* node) {
-  VisitMinOrMax(this, node, kX64F64x4Pmax, true);
-}
-
 template <typename Adapter>
 void InstructionSelectorT<Adapter>::VisitF32x4RelaxedMin(Node* node) {
   VisitMinOrMax(this, node, kX64Minps, false);

src/compiler/machine-operator.cc

@@ -774,8 +774,6 @@ std::ostream& operator<<(std::ostream& os, TruncateKind kind) {
   V(I32x8ExtAddPairwiseI16x16U, Operator::kNoProperties, 1, 0, 1)          \
   V(I16x16ExtAddPairwiseI8x32S, Operator::kNoProperties, 1, 0, 1)          \
   V(I16x16ExtAddPairwiseI8x32U, Operator::kNoProperties, 1, 0, 1)          \
-  V(F64x4Pmin, Operator::kNoProperties, 2, 0, 1)                           \
-  V(F64x4Pmax, Operator::kNoProperties, 2, 0, 1)                           \
   V(S256Zero, Operator::kNoProperties, 0, 0, 1)                            \
   V(S256And, Operator::kAssociative | Operator::kCommutative, 2, 0, 1)     \
   V(S256Or, Operator::kAssociative | Operator::kCommutative, 2, 0, 1)      \

src/compiler/machine-operator.h

@@ -1111,8 +1111,6 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
   const Operator* I32x8Splat();
   const Operator* I16x16Splat();
   const Operator* I8x32Splat();
-  const Operator* F64x4Pmin();
-  const Operator* F64x4Pmax();
 
   const Operator* S256Zero();
   const Operator* S256And();

src/compiler/opcodes.h

@@ -1213,9 +1213,7 @@
   V(I64x4Splat)                    \
   V(I32x8Splat)                    \
   V(I16x16Splat)                   \
-  V(I8x32Splat)                    \
-  V(F64x4Pmin)                     \
-  V(F64x4Pmax)
+  V(I8x32Splat)
 
 #define VALUE_OP_LIST(V)     \
   COMMON_OP_LIST(V)          \

src/compiler/revectorizer.cc

@@ -534,11 +534,7 @@ PackNode* SLPTree::BuildTree(const ZoneVector<Node*>& roots) {
   V(I8x16GeS, I8x32GeS)    \
   V(I32x4GeU, I32x8GeU)    \
   V(I16x8GeU, I16x16GeU)   \
-  V(I8x16GeU, I8x32GeU)    \
-  V(F32x4Pmin, F32x8Pmin)  \
-  V(F32x4Pmax, F32x8Pmax)  \
-  V(F64x2Pmin, F64x4Pmin)  \
-  V(F64x2Pmax, F64x4Pmax)
+  V(I8x16GeU, I8x32GeU)
 
 #define SIMD_SHIFT_OP(V)   \
   V(I64x2Shl, I64x4Shl)    \

test/cctest/wasm/test-run-wasm-simd.cc

@@ -439,26 +439,6 @@ WASM_EXEC_TEST(F32x4Pmax) {
   RunF32x4BinOpTest(execution_tier, kExprF32x4Pmax, Maximum);
 }
 
-#ifdef V8_ENABLE_WASM_SIMD256_REVEC
-TEST(RunWasmTurbofan_F32x8Min) {
-  RunF32x8BinOpRevecTest(kExprF32x4Min, JSMin, compiler::IrOpcode::kF32x8Min);
-}
-
-TEST(RunWasmTurbofan_F32x8Max) {
-  RunF32x8BinOpRevecTest(kExprF32x4Max, JSMax, compiler::IrOpcode::kF32x8Max);
-}
-
-TEST(RunWasmTurbofan_F32x8Pmin) {
-  RunF32x8BinOpRevecTest(kExprF32x4Pmin, Minimum,
-                         compiler::IrOpcode::kF32x8Pmin);
-}
-
-TEST(RunWasmTurbofan_F32x8Pmax) {
-  RunF32x8BinOpRevecTest(kExprF32x4Pmax, Maximum,
-                         compiler::IrOpcode::kF32x8Pmax);
-}
-#endif  // V8_ENABLE_WASM_SIMD256_REVEC
-
 WASM_EXEC_TEST(F32x4Eq) {
   RunF32x4CompareOpTest(execution_tier, kExprF32x4Eq, Equal);
 }
@@ -1058,26 +1038,6 @@ WASM_EXEC_TEST(F64x2Pmax) {
   RunF64x2BinOpTest(execution_tier, kExprF64x2Pmax, Maximum);
 }
 
-#ifdef V8_ENABLE_WASM_SIMD256_REVEC
-TEST(RunWasmTurbofan_F64x4Min) {
-  RunF64x4BinOpRevecTest(kExprF64x2Min, JSMin, compiler::IrOpcode::kF64x4Min);
-}
-
-TEST(RunWasmTurbofan_F64x4Max) {
-  RunF64x4BinOpRevecTest(kExprF64x2Max, JSMax, compiler::IrOpcode::kF64x4Max);
-}
-
-TEST(RunWasmTurbofan_F64x4Pmin) {
-  RunF64x4BinOpRevecTest(kExprF64x2Pmin, Minimum,
-                         compiler::IrOpcode::kF64x4Pmin);
-}
-
-TEST(RunWasmTurbofan_F64x4Pmax) {
-  RunF64x4BinOpRevecTest(kExprF64x2Pmax, Maximum,
-                         compiler::IrOpcode::kF64x4Pmax);
-}
-#endif  // V8_ENABLE_WASM_SIMD256_REVEC
-
 WASM_EXEC_TEST(F64x2Eq) {
   RunF64x2CompareOpTest(execution_tier, kExprF64x2Eq, Equal);
 }

test/cctest/wasm/wasm-simd-utils.cc

@@ -1127,86 +1127,6 @@ void RunF32x4BinOpTest(TestExecutionTier execution_tier, WasmOpcode opcode,
   }
 }
 
-#ifdef V8_ENABLE_WASM_SIMD256_REVEC
-void RunF32x8BinOpRevecTest(WasmOpcode opcode, FloatBinOp expected_op,
-                            compiler::IrOpcode::Value revec_opcode) {
-  EXPERIMENTAL_FLAG_SCOPE(revectorize);
-  WasmRunner<int32_t, int32_t, int32_t, int32_t> r(
-      TestExecutionTier::kTurbofan);
-  float* memory = r.builder().AddMemoryElems<float>(24);
-  // Build fn perform binary operation on two 256 bit vectors a and b,
-  // store the result in c:
-  //   simd128 *a,*b,*c;
-  //   *c = *a bin_op *b;
-  //   *(c+1) = *(a+1) bin_op *(b+1);
-  uint8_t param1 = 0;
-  uint8_t param2 = 1;
-  uint8_t param3 = 2;
-  uint8_t temp1 = r.AllocateLocal(kWasmS128);
-  uint8_t temp2 = r.AllocateLocal(kWasmS128);
-  constexpr uint8_t offset = 16;
-
-  BUILD_AND_CHECK_REVEC_NODE(
-      r, revec_opcode,
-      WASM_LOCAL_SET(
-          temp1,
-          WASM_SIMD_BINOP(opcode, WASM_SIMD_LOAD_MEM(WASM_LOCAL_GET(param1)),
-                          WASM_SIMD_LOAD_MEM(WASM_LOCAL_GET(param2)))),
-      WASM_LOCAL_SET(
-          temp2,
-          WASM_SIMD_BINOP(
-              opcode, WASM_SIMD_LOAD_MEM_OFFSET(offset, WASM_LOCAL_GET(param1)),
-              WASM_SIMD_LOAD_MEM_OFFSET(offset, WASM_LOCAL_GET(param2)))),
-      WASM_SIMD_STORE_MEM(WASM_LOCAL_GET(param3), WASM_LOCAL_GET(temp1)),
-      WASM_SIMD_STORE_MEM_OFFSET(offset, WASM_LOCAL_GET(param3),
-                                 WASM_LOCAL_GET(temp2)),
-      WASM_ONE);
-
-  FOR_FLOAT32_INPUTS(x) {
-    if (!PlatformCanRepresent(x)) continue;
-    FOR_FLOAT32_INPUTS(y) {
-      if (!PlatformCanRepresent(y)) continue;
-      if (ShouldSkipTestingConstants(opcode, x, y)) continue;
-      float expected = expected_op(x, y);
-      if (!PlatformCanRepresent(expected)) continue;
-      for (int i = 0; i < 4; i++) {
-        r.builder().WriteMemory(&memory[i], x);
-        r.builder().WriteMemory(&memory[i + 4], x);
-        r.builder().WriteMemory(&memory[i + 8], y);
-        r.builder().WriteMemory(&memory[i + 12], y);
-      }
-      r.Call(0, 32, 64);
-      for (int i = 0; i < 4; i++) {
-        CheckFloatResult(x, y, expected, memory[i + 16], true /* exact */);
-        CheckFloatResult(x, y, expected, memory[i + 20], true /* exact */);
-      }
-    }
-  }
-
-  FOR_FLOAT32_NAN_INPUTS(f) {
-    float x = base::bit_cast<float>(nan_test_array[f]);
-    if (!PlatformCanRepresent(x)) continue;
-    FOR_FLOAT32_NAN_INPUTS(j) {
-      float y = base::bit_cast<float>(nan_test_array[j]);
-      if (!PlatformCanRepresent(y)) continue;
-      float expected = expected_op(x, y);
-      if (!PlatformCanRepresent(expected)) continue;
-      for (int i = 0; i < 4; i++) {
-        r.builder().WriteMemory(&memory[i], x);
-        r.builder().WriteMemory(&memory[i + 4], x);
-        r.builder().WriteMemory(&memory[i + 8], y);
-        r.builder().WriteMemory(&memory[i + 12], y);
-      }
-      r.Call(0, 32, 64);
-      for (int i = 0; i < 4; i++) {
-        CheckFloatResult(x, y, expected, memory[i + 16], true /* exact */);
-        CheckFloatResult(x, y, expected, memory[i + 20], true /* exact */);
-      }
-    }
-  }
-}
-#endif
-
 void RunF32x4CompareOpTest(TestExecutionTier execution_tier, WasmOpcode opcode,
                            FloatCompareOp expected_op) {
   WasmRunner<int32_t, float, float> r(execution_tier);
@@ -1430,86 +1350,6 @@ void RunF64x2BinOpTest(TestExecutionTier execution_tier, WasmOpcode opcode,
   }
 }
 
-#ifdef V8_ENABLE_WASM_SIMD256_REVEC
-void RunF64x4BinOpRevecTest(WasmOpcode opcode, DoubleBinOp expected_op,
-                            compiler::IrOpcode::Value revec_opcode) {
-  EXPERIMENTAL_FLAG_SCOPE(revectorize);
-  WasmRunner<int32_t, int32_t, int32_t, int32_t> r(
-      TestExecutionTier::kTurbofan);
-  double* memory = r.builder().AddMemoryElems<double>(12);
-  // Build fn perform binary operation on two 256 bit vectors a and b,
-  // store the result in c:
-  //   simd128 *a,*b,*c;
-  //   *c = *a bin_op *b;
-  //   *(c+1) = *(a+1) bin_op *(b+1);
-  uint8_t param1 = 0;
-  uint8_t param2 = 1;
-  uint8_t param3 = 2;
-  uint8_t temp1 = r.AllocateLocal(kWasmS128);
-  uint8_t temp2 = r.AllocateLocal(kWasmS128);
-  constexpr uint8_t offset = 16;
-
-  BUILD_AND_CHECK_REVEC_NODE(
-      r, revec_opcode,
-      WASM_LOCAL_SET(
-          temp1,
-          WASM_SIMD_BINOP(opcode, WASM_SIMD_LOAD_MEM(WASM_LOCAL_GET(param1)),
-                          WASM_SIMD_LOAD_MEM(WASM_LOCAL_GET(param2)))),
-      WASM_LOCAL_SET(
-          temp2,
-          WASM_SIMD_BINOP(
-              opcode, WASM_SIMD_LOAD_MEM_OFFSET(offset, WASM_LOCAL_GET(param1)),
-              WASM_SIMD_LOAD_MEM_OFFSET(offset, WASM_LOCAL_GET(param2)))),
-      WASM_SIMD_STORE_MEM(WASM_LOCAL_GET(param3), WASM_LOCAL_GET(temp1)),
-      WASM_SIMD_STORE_MEM_OFFSET(offset, WASM_LOCAL_GET(param3),
-                                 WASM_LOCAL_GET(temp2)),
-      WASM_ONE);
-
-  FOR_FLOAT64_INPUTS(x) {
-    if (!PlatformCanRepresent(x)) continue;
-    FOR_FLOAT64_INPUTS(y) {
-      if (!PlatformCanRepresent(y)) continue;
-      if (ShouldSkipTestingConstants(opcode, x, y)) continue;
-      double expected = expected_op(x, y);
-      if (!PlatformCanRepresent(expected)) continue;
-      for (int i = 0; i < 2; i++) {
-        r.builder().WriteMemory(&memory[i], x);
-        r.builder().WriteMemory(&memory[i + 2], x);
-        r.builder().WriteMemory(&memory[i + 4], y);
-        r.builder().WriteMemory(&memory[i + 6], y);
-      }
-      r.Call(0, 32, 64);
-      for (int i = 0; i < 2; i++) {
-        CheckDoubleResult(x, y, expected, memory[i + 8], true /* exact */);
-        CheckDoubleResult(x, y, expected, memory[i + 10], true /* exact */);
-      }
-    }
-  }
-
-  FOR_FLOAT64_NAN_INPUTS(f) {
-    double x = base::bit_cast<double>(double_nan_test_array[f]);
-    if (!PlatformCanRepresent(x)) continue;
-    FOR_FLOAT64_NAN_INPUTS(j) {
-      double y = base::bit_cast<double>(double_nan_test_array[j]);
-      if (!PlatformCanRepresent(y)) continue;
-      double expected = expected_op(x, y);
-      if (!PlatformCanRepresent(expected)) continue;
-      for (int i = 0; i < 2; i++) {
-        r.builder().WriteMemory(&memory[i], x);
-        r.builder().WriteMemory(&memory[i + 2], x);
-        r.builder().WriteMemory(&memory[i + 4], y);
-        r.builder().WriteMemory(&memory[i + 6], y);
-      }
-      r.Call(0, 32, 64);
-      for (int i = 0; i < 2; i++) {
-        CheckDoubleResult(x, y, expected, memory[i + 8], true /* exact */);
-        CheckDoubleResult(x, y, expected, memory[i + 10], true /* exact */);
-      }
-    }
-  }
-}
-#endif
-
 void RunF64x2CompareOpTest(TestExecutionTier execution_tier, WasmOpcode opcode,
                            DoubleCompareOp expected_op) {
   WasmRunner<int32_t, double, double> r(execution_tier);

test/cctest/wasm/wasm-simd-utils.h

@@ -260,10 +260,6 @@ void RunI32x8BinOpRevecTest(WasmOpcode opcode, OpType expected_op,
 
 void RunI64x4BinOpRevecTest(WasmOpcode opcode, Int64BinOp expected_op,
                             compiler::IrOpcode::Value revec_opcode);
-void RunF64x4BinOpRevecTest(WasmOpcode opcode, DoubleBinOp expected_op,
-                            compiler::IrOpcode::Value revec_opcode);
-void RunF32x8BinOpRevecTest(WasmOpcode opcode, FloatBinOp expected_op,
-                            compiler::IrOpcode::Value revec_opcode);
 
 void RunI16x16ShiftOpRevecTest(WasmOpcode opcode, Int16ShiftOp expected_op,
                                compiler::IrOpcode::Value revec_opcode);