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"Bridging the Nanosecond Gap: From High-Precision Silicon & Power Hardware to Low-Latency Quantitative Execution."
My engineering background converges at the intersection of hardware silicon & embedded power systems and high-throughput quantitative execution architectures, delivering end-to-end solutions from physical schematics to algorithmic software:
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Hardware Engineering, Mixed-Signal Silicon & Power Systems:
- Precision Analog Front-End (AFE) Design: Low-noise biopotential acquisition stages with CMRR >100 dB, laser-trimmed instrumentation amplifiers, and active Driven Right Leg (DRL) noise suppression.
- High-Power Motor Drives & Power Electronics: High-voltage, high-current 3-Phase BLDC motor drive inverters (84V / 40A, TEKNOFEST 2023 3rd & 9th Place), closed-loop Switch-Mode Power Supplies (SMPS Buck/Boost), and state-space analog PI compensators.
- Digital FPGA RTL Design & Automated DAQ: Synthesizable streaming architectures (SystemVerilog / Verilog on Xilinx Vivado) with AXI4-Stream bus flow control, paired with automated virtual instrumentation suites (LabVIEW / 16-bit SAR ADC dynamic characterization).
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Quantitative Systems, Microstructure & Low-Latency Software:
- Market Microstructure & Order Flow Analysis: Modeling tick-level Order Flow Imbalance (OFI), Level-2 limit order book liquidity dynamics, and information-driven volume/dollar bar sampling pipelines.
- Convex Portfolio Risk Optimization: Deploying machine-learning tree clustering algorithms (Hierarchical Risk Parity - HRP), Conditional Drawdown-at-Risk (CDaR), and Extreme Value Theory (EVT / VaR / Expected Shortfall) tail-risk shields.
- High-Performance Deterministic Execution: Building low-latency, thread-safe financial execution pipelines and dynamic state tracking engines utilizing Modern C++ (C++17/20) and vectorized scientific Python (NumPy, Polars, SciPy).
┌───────────────────────────────────────────────┐
│ MUSTAFA YAĞCI │
└───────────────────────┬───────────────────────┘
│
┌─────────────────────────────────────┴─────────────────────────────────────┐
▼ ▼
┌─────────────────────────────────────────┐ ┌─────────────────────────────────────────┐
│ HARDWARE, SILICON & POWER SYSTEMS │ │ QUANTITATIVE & LOW-LATENCY SYSTEMS │
├─────────────────────────────────────────┤ ├─────────────────────────────────────────┤
│ • High-Power BLDC Inverters (84V / 40A) │ │ • Market Microstructure & Order Flow │
│ • Mixed-Signal PCB & Low-Noise AFE │ │ • Dollar/Volume Sampling & Trade Bars │
│ • Instrumentation Stages (CMRR >100 dB) │ │ • Convex Portfolio Optimization (HRP) │
│ • FPGA RTL Synthesis (Vivado / AXI4) │ │ • Extreme Value Theory (EVT & VaR) │
│ • Switch-Mode Power (Buck/Boost / PSIM) │ │ • High-Throughput Modern C++20 & Python │
│ • Automated Virtual DAQ & ADC Testing │ │ • Low-Latency Execution Architecture │
└─────────────────────────────────────────┘ └─────────────────────────────────────────┘
⚡ High-Power BLDC Motor Driver🎓 B.Sc. Capstone Graduation Thesis & EV Propulsion Inverter Industrial 84V / 40A 3-phase sensored BLDC motor controller engineered for EV propulsion:
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🧬 unipa-bioamp-proPrecision Biomedical Analog Front-End & Solid Ground Shield (KiCad 8) Custom biomedical biopotential acquisition board (ECG/EMG/EEG) engineered from first principles:
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🏛️ engineering-academic-portfolioUndergraduate (B.Sc. Graduated) & Master's (M.Sc. Student, Ongoing) Practicum Archive Complete historical archive of 94 files (~50 MB) across 6 years of laboratory research, industrial automation, and simulation models:
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⚡ microstructure-dollar-bars-engineTick-Level Flow Imbalance & Rolling Kalman Filter Ultra-low-latency financial time series processor and market state estimation engine:
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| Domain | Technologies, Frameworks & Tooling |
|---|---|
| EDA & Hardware Design |
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| Languages & HDL |
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| Quantitative & Scientific |
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| Protocols & Interfaces |
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| Applied Standards |
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- Email: mrmustafayagci@gmail.com
- LinkedIn: Mustafa Yağcı
- Academic Affiliation: Università degli Studi di Palermo (UniPa), M.Sc. Student in Electronic Engineering (Nov 2025 – Present / Ongoing)