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i try to compile the code, but failed.
verilator --error-limit 10 -j 16 --timescale-override "1ns/1ns" --trace-max-array 64 -cc --threads 7 --top-module chip --autoflush -CFLAGS "-g" -LDFLAGS "-g" -Wno-lint +1800-2017ext+sv -o svv +define+SIMV +define+SIMD +define+VSYNTH +define+VSYNTH2 +define+NALU3 +define+COMBINED_BRANCH +define+RENAME_OPT cpu.sv decode.sv rename.sv commit.sv alu.sv shift.sv mul.sv alu_ctrl.sv csr.sv pc.sv bpred.sv dtlb.sv itlb.sv ls.sv dc1.sv ic1.sv fetch.sv tlbf.sv tc2.sv pmap.sv boot0.sv boot1.sv chip.sv mi.sv ioi.sv rvtimer.sv clic.sv plic.sv dtbrom.sv rviodtb.sv rvsd.sv rvgpio.sv mmem.sv rfile_21_1_9_1_8_32_4.sv +incdir+uart rvuart.sv uart/raminfr.v uart/uart_receiver.v uart/uart_regs.v uart/uart_rfifo.v uart/uart_sync_flops.v uart/uart_tfifo.v uart/uart_top.v uart/uart_transmitter.v uart/uart_wb.v synth/vsram.v +define+NALU3 +define+COMBINED_BRANCH +define+RENAME_OPT --assert --clk clk --trace -sv --compiler gcc -exe testbench.cpp
%Error: Internal Error: mk21_32_6_4_4_32.inc:3289:32: ../V3LinkDot.cpp:2491: Couldn't resolve inlined scope 'genblk2[0]' in: chip.c__BRA__0__KET____DOT__cpu.load_store.genblk1__DOT__genblk2__BRA__0__KET__
3289 | r_load_enable[3] & dc_load.ack[3].hit & (dc_rd_hart[3] == H) & dc_rd_lr[3] & !load_allocate[3] & !r_load_sc[3],
| ^~~
ls.sv:559:81: ... note: In file included from ls.sv
... See the manual at https://verilator.org/verilator_doc.html for more assistance.
make: *** [Makefile:172: obj_dir/svv] Error 1
i am using v4.212 verilator.
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