A SystemC/CRAVE based Contrained Random Instruction Generator
To achieve high test coverage, a co-simulation approach uses often randomly generated instruction streams. By defining appropriate constraints, a generator can enforce and check properties that span multiple instructions.
This approach offers several advantages. Existing methods for extracting microarchitectural invariants—used to prove functional correctness—often require substantial manual effort, such as translating specifications into SVA or modeling instruction behavior
By contrast, this project will leverage the machine-readable ISAX specifications in CoreDSL, defined by partners in the BMBF project Scale4Edge. This enables a more efficient and better integrated open-source toolflow.
This is the very first version of the CRAVE based instruction stream generator (ISG). It does not yet build standalone rather only as part of a SystemC based verification project.