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use Chisel version 6.1.0
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@Martoni
Martoni committed Mar 7, 2024
1 parent 55d21aa commit 1595d6d
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Showing 6 changed files with 128 additions and 19 deletions.
18 changes: 9 additions & 9 deletions build.sbt
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Original file line number Diff line number Diff line change
@@ -1,27 +1,27 @@
// See README.md for license details.

scalaVersion := "2.13.8"
version := "0.2.2"
scalaVersion := "2.13.12"
version := "6.1.0"
organization := "Martoni"

val majorChiselVersion = "3"
val minorChiselVersion = "5.6"
val majorChiselVersion = "6"
val minorChiselVersion = "1.0"

val chiselVersion = majorChiselVersion + "." + minorChiselVersion

lazy val root = (project in file("."))
.settings(
name := "fpgamacro",
libraryDependencies ++= Seq(
"edu.berkeley.cs" %% "chisel3" % chiselVersion,
"edu.berkeley.cs" %% "chiseltest" % ("0." + minorChiselVersion) % "test"
"org.chipsalliance" %% "chisel" % chiselVersion,
"org.scalatest" %% "scalatest" % "3.2.16" % "test",
),
scalacOptions ++= Seq(
"-Xsource:2.11",
"-language:reflectiveCalls",
"-deprecation",
"-feature",
"-Xcheckinit"
"-Xcheckinit",
"-Ymacro-annotations",
),
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full),
addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full),
)
1 change: 0 additions & 1 deletion project/plugin.sbt
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6 changes: 0 additions & 6 deletions src/main/scala/fpgamacro/ecp5/ecp5.scala
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This file was deleted.

94 changes: 93 additions & 1 deletion src/main/scala/fpgamacro/eos_s3/eos_s3.scala
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
package fpgamacro.eos_s3

import chisel3._
import circt.stage.ChiselStage
import chisel3.util._
import chisel3.experimental.Analog

Expand Down Expand Up @@ -91,6 +92,48 @@ class SysClk extends RawModule {
})
val u_qlal4s3b_cell_macro = Module(new qlal4s3b_cell_macro())
io.sys_clk_0 := u_qlal4s3b_cell_macro.io.Sys_Clk0

/* DontCare */
u_qlal4s3b_cell_macro.io.WB_CLK := DontCare
u_qlal4s3b_cell_macro.io.WBs_RD_DAT := DontCare
u_qlal4s3b_cell_macro.io.WBs_ACK := DontCare
u_qlal4s3b_cell_macro.io.SDMA_Req := DontCare
u_qlal4s3b_cell_macro.io.SDMA_Sreq := DontCare
u_qlal4s3b_cell_macro.io.FB_msg_out := DontCare
u_qlal4s3b_cell_macro.io.FB_Int_Clr := DontCare
u_qlal4s3b_cell_macro.io.FB_Busy := DontCare
u_qlal4s3b_cell_macro.io.Sys_PKfb_Clk := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbData := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbPush := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbSOF := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbEOF := DontCare
u_qlal4s3b_cell_macro.io.Sys_PSel := DontCare
u_qlal4s3b_cell_macro.io.SPIm_Paddr := DontCare
u_qlal4s3b_cell_macro.io.SPIm_PEnable := DontCare
u_qlal4s3b_cell_macro.io.SPIm_PWrite := DontCare
u_qlal4s3b_cell_macro.io.SPIm_PWdata := DontCare
u_qlal4s3b_cell_macro.io.Device_ID := DontCare
u_qlal4s3b_cell_macro.io.FBIO_In_En := DontCare
u_qlal4s3b_cell_macro.io.FBIO_Out := DontCare
u_qlal4s3b_cell_macro.io.FBIO_Out_En := DontCare
u_qlal4s3b_cell_macro.io.Device_ID_6S := DontCare
u_qlal4s3b_cell_macro.io.Device_ID_4S := DontCare
u_qlal4s3b_cell_macro.io.SPIm_PWdata_26S := DontCare
u_qlal4s3b_cell_macro.io.SPIm_PWdata_24S := DontCare
u_qlal4s3b_cell_macro.io.SPIm_PWdata_14S := DontCare
u_qlal4s3b_cell_macro.io.SPIm_PWdata_11S := DontCare
u_qlal4s3b_cell_macro.io.SPIm_PWdata_0S := DontCare
u_qlal4s3b_cell_macro.io.SPIm_Paddr_8S := DontCare
u_qlal4s3b_cell_macro.io.SPIm_Paddr_6S := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbPush_1S := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbData_31S := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbData_21S := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbData_19S := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbData_9S := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbData_6S := DontCare
u_qlal4s3b_cell_macro.io.Sys_PKfb_ClkS := DontCare
u_qlal4s3b_cell_macro.io.FB_BusyS := DontCare
u_qlal4s3b_cell_macro.io.WB_CLKS := DontCare
}

class SysClkAndRst extends RawModule {
Expand All @@ -101,10 +144,59 @@ class SysClkAndRst extends RawModule {
val u_qlal4s3b_cell_macro = Module(new qlal4s3b_cell_macro())
io.sys_clk_0 := u_qlal4s3b_cell_macro.io.Sys_Clk0
io.sys_clk_0_rst := u_qlal4s3b_cell_macro.io.Sys_Clk0_Rst

/* DontCare */
u_qlal4s3b_cell_macro.io.WB_CLK := DontCare
u_qlal4s3b_cell_macro.io.WBs_RD_DAT := DontCare
u_qlal4s3b_cell_macro.io.WBs_ACK := DontCare
u_qlal4s3b_cell_macro.io.SDMA_Req := DontCare
u_qlal4s3b_cell_macro.io.SDMA_Sreq := DontCare
u_qlal4s3b_cell_macro.io.FB_msg_out := DontCare
u_qlal4s3b_cell_macro.io.FB_Int_Clr := DontCare
u_qlal4s3b_cell_macro.io.FB_Busy := DontCare
u_qlal4s3b_cell_macro.io.Sys_PKfb_Clk := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbData := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbPush := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbSOF := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbEOF := DontCare
u_qlal4s3b_cell_macro.io.Sys_PSel := DontCare
u_qlal4s3b_cell_macro.io.SPIm_Paddr := DontCare
u_qlal4s3b_cell_macro.io.SPIm_PEnable := DontCare
u_qlal4s3b_cell_macro.io.SPIm_PWrite := DontCare
u_qlal4s3b_cell_macro.io.SPIm_PWdata := DontCare
u_qlal4s3b_cell_macro.io.Device_ID := DontCare
u_qlal4s3b_cell_macro.io.FBIO_In_En := DontCare
u_qlal4s3b_cell_macro.io.FBIO_Out := DontCare
u_qlal4s3b_cell_macro.io.FBIO_Out_En := DontCare
u_qlal4s3b_cell_macro.io.Device_ID_6S := DontCare
u_qlal4s3b_cell_macro.io.Device_ID_4S := DontCare
u_qlal4s3b_cell_macro.io.SPIm_PWdata_26S := DontCare
u_qlal4s3b_cell_macro.io.SPIm_PWdata_24S := DontCare
u_qlal4s3b_cell_macro.io.SPIm_PWdata_14S := DontCare
u_qlal4s3b_cell_macro.io.SPIm_PWdata_11S := DontCare
u_qlal4s3b_cell_macro.io.SPIm_PWdata_0S := DontCare
u_qlal4s3b_cell_macro.io.SPIm_Paddr_8S := DontCare
u_qlal4s3b_cell_macro.io.SPIm_Paddr_6S := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbPush_1S := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbData_31S := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbData_21S := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbData_19S := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbData_9S := DontCare
u_qlal4s3b_cell_macro.io.FB_PKfbData_6S := DontCare
u_qlal4s3b_cell_macro.io.Sys_PKfb_ClkS := DontCare
u_qlal4s3b_cell_macro.io.FB_BusyS := DontCare
u_qlal4s3b_cell_macro.io.WB_CLKS := DontCare
}

object SysClkAndRst extends App {
(new chisel3.stage.ChiselStage).emitVerilog(new SysClkAndRst(), args)
val verilog_src = ChiselStage.emitSystemVerilog(
new SysClkAndRst(),
firtoolOpts = Array("-disable-all-randomization",
"-strip-debug-info"))
val fverilog = os.pwd / "SysClkAndRst.v"
if(os.exists(fverilog))
os.remove(fverilog)
os.write(fverilog, verilog_src)
}

// TODO: integrate this macro in chisel
Expand Down
10 changes: 9 additions & 1 deletion src/main/scala/fpgamacro/gatemate/PLL.scala
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
package fpgamacro.gatemate

import chisel3._
import circt.stage.ChiselStage
import chisel3.util.Cat
import chisel3.experimental.Param

Expand Down Expand Up @@ -71,5 +72,12 @@ class TopCC_PLL extends RawModule {
}

object TopCC_PLL extends App {
(new chisel3.stage.ChiselStage).emitVerilog(new TopCC_PLL(), args)
val verilog_src = ChiselStage.emitSystemVerilog(
new TopCC_PLL(),
firtoolOpts = Array("-disable-all-randomization",
"-strip-debug-info"))
val fverilog = os.pwd / "TopCC_PLL.v"
if(os.exists(fverilog))
os.remove(fverilog)
os.write(fverilog, verilog_src)
}
18 changes: 17 additions & 1 deletion src/main/scala/fpgamacro/ice40/PLL_ICE40.scala
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
package fpgamacro.ice40

import chisel3._
import circt.stage.ChiselStage
import chisel3.util._
import chisel3.experimental.Param

Expand Down Expand Up @@ -83,8 +84,23 @@ class TopSB_PLL40_CORE extends RawModule {
io.clock_o := gm_pll.io.PLLOUTCORE
gm_pll.io.RESETB := true.B
gm_pll.io.BYPASS := false.B

gm_pll.io.EXTFEEDBACK := DontCare

gm_pll.io.DYNAMICDELAY := DontCare
gm_pll.io.LATCHINPUTVALUE := DontCare
gm_pll.io.SDI := DontCare
gm_pll.io.SCLK := DontCare
}

object TopSB_PLL40_CORE extends App {
(new chisel3.stage.ChiselStage).emitVerilog(new TopSB_PLL40_CORE(), args)
val verilog_src = ChiselStage.emitSystemVerilog(
new TopSB_PLL40_CORE(),
firtoolOpts = Array("-disable-all-randomization",
"-strip-debug-info"))
val fverilog = os.pwd / "TopSB_PLL40_CORE.v"
if(os.exists(fverilog))
os.remove(fverilog)
os.write(fverilog, verilog_src)
}

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