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A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

Verilog 117 24 Updated Dec 2, 2019

FreeRTOS adaptation for CMSIS-RTOS Version 2

C 534 141 Updated Aug 19, 2024

ArduPlane, ArduCopter, ArduRover, ArduSub source

C++ 11,003 17,542 Updated Nov 12, 2024

A professional cross-platform SSH/Sftp/Shell/Telnet/Serial terminal.

C 23,321 1,799 Updated Apr 3, 2024

micro riscv

Verilog 1 Updated Jun 16, 2022

Very slow implementation of riscv. Made for the lulz.

Verilog 4 Updated Nov 10, 2018

Run any open-source LLMs, such as Llama, Gemma, as OpenAI compatible API endpoint in the cloud.

Python 10,038 636 Updated Nov 11, 2024

The next generation of OpenLane, rewritten from scratch with a modular architecture

Python 207 38 Updated Nov 10, 2024

Open source SDR 4G software suite from Software Radio Systems (SRS) https://docs.srsran.com/projects/4g

C++ 3,481 1,146 Updated Jun 17, 2024

CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

C 1,094 103 Updated Oct 24, 2024

GSM+GPRS Radio Access Network Node reloaded for 2024 for newest UHD drivers and supporting Ubuntu 22.04

C++ 143 32 Updated Jul 4, 2024

GitHub Repository for iotSDR open source material

Jupyter Notebook 31 11 Updated Feb 28, 2024

AstroNvim is an aesthetic and feature-rich neovim config that is extensible and easy to use with a great set of plugins

Lua 12,743 926 Updated Nov 8, 2024

Windows inside a Docker container.

Shell 27,185 1,902 Updated Nov 13, 2024

CORE-V Family of RISC-V Cores

206 15 Updated Feb 15, 2024

Versatile, cheap and portable USB to GPIB converter (USBTMC class based)

HTML 288 51 Updated Jun 4, 2024

Various HDL (Verilog) IP Cores

Verilog 707 215 Updated Jul 1, 2021

Verilog UART

Verilog 420 129 Updated Mar 21, 2023

The Dom amongst the Flipper Zero Firmware. Give your Flipper the power and freedom it is really craving. Let it show you its true form. Dont delay, switch to the one and only true Master today!

C 9,475 693 Updated Jun 29, 2024

The BLHeli_S open source sensorless brushless motor electronic speed control (ESC) firmware.

Assembly 77 21 Updated Mar 15, 2020

Firmware for stm32f051 based speed controllers for use with mutirotors

C 820 286 Updated Jul 25, 2024

Comically fast Dota 2, CSGO, CS2 and Deadlock replay parser written in Java.

Java 662 121 Updated Sep 21, 2024

V2 of the fantastic Raspberry Pi NOAA setup

Jinja 558 103 Updated Oct 26, 2024

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog 2,117 285 Updated Nov 12, 2024

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,140 755 Updated Jun 27, 2024

GNU toolchain for RISC-V, including GCC

C 3,536 1,165 Updated Nov 7, 2024

Neovim config for the lazy

Lua 17,331 1,227 Updated Nov 11, 2024

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

Assembly 527 43 Updated Jan 4, 2024

πŸ–₯️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

VHDL 1,594 225 Updated Nov 12, 2024

SERV - The SErial RISC-V CPU

Verilog 1,438 189 Updated Nov 11, 2024
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