Hardware Acceleration using FPGA for Floating-Point Arithmetic

Full design implemented on FPGA also included use of SDRAM, NIOS II/f soft processor, JTAG, as well as some other miscellaneous components.

Design was implemented using Quartus II.

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32-bit Addition, Subtraction, and Multiplication using IEEE-754 Floating-Point standard.

Note that it does not implement handling of +inf and -inf values.

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CORDIC Algorithm implemented in Verilog for use with 22-bit fixed-point (1 sign bit, 1 integer bit, followed by 20 fractional bits. Can be changed to be done in 16 to 1 iterations by modifying loop condition.

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Note that less iterations might require slower clock or better FPGA.

Conversions between 32-bit Floating-Point and 22-bit fixed-point included with custom made files made in Verilog.

Note that converting Floating-Point to Fixed-Point and vice versa incurs precision loss.

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All custom made Verilog modules could complete execution in 1 clock cycle using an Intel Altera Cyclone V 5CSEMA5F31C6N FPGA clocked @ 50 MHz.

Note that the CORDIC module was discovered to only be able to complete execution in 4 clock cycles or more in order to not violate timing on the FPGA.

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Top file in main folder calculates 0.5 * X + X^2 * cos((X - 128) / 128) as a test of the overall function.

It includes instances of 1 Adder module, 4 Multiplication modules, 1 Subtraction module, 1 CORDIC Module, 1 Fixed-To-Float Module, and 1 Float-to-Fixed Module.

For the following ModelSim picture, the CORDIC is set at 4 iterations per clock cycle.

Gallery contains ModelSim screenshots of the different Verilog modules.

In Extra_Implementations folder there can be found additional special implementations of CORDIC as well as the regular top file. e.g. Pipelined CORDIC and multi-input modules.