A Verilog project that implements and tests two cache organizations: Direct Mapped cache and Fully Associative cache.
a. L1 Data Cache - 32 KB.
b. Cache Block Size - 64 bytes.
c. Memory- 64 KB.
d. Cache <-> Memory Bus width - 64 bits.
e. Memory Bus Speed - 200 MHz.
Both caches connect to the same 64 KB backing memory model (implemented using Block RAM ip) and are write back in nature, burst fills/writebacks are (8 x 64 bit beats per 64 byte line), and a fixed line size of 64 B.
Two testbenches drive row major and column major matrix walks, measure misses, hits, writebacks, and compute bus traffic between cache and memory.
The row and column major loops are as follows:
Direct-Mapped Cache (32x32 matrix size):
Direct-Mapped Cache (128x128 matrix size):
Fully Associative Cache with Random Replacement (32x32 matrix size):
Fully Associative Cache with Random Replacement (128x128 matrix size):
Fully Associative Cache with LRU Replacement (128x128 matrix size):
