feat(debug): add direct DMI and drain halt/reset transactions

[murdoa]

What changes

Add an optional synchronous direct-DMI frontend, selected at elaboration instead of JTAG. Each asserted request edge accesses one DM register; reads are combinational before the edge. JTAG remains the default. There is no queued transport response, ready/valid interface or runtime handover.

Fix related halt and DM ownership problems:

• Drain the current lockstep instruction before external halt. Previously, halt/resume could repeat completed MMIO reads/stores, or save the retiring instruction's PC instead of its branch/compressed successor. Preserve one-cycle halt requests and debugger register edits.
• Acknowledge completed resume, preserve halt priority, and prevent abstract-command/data replacement while busy. Keep command errors sticky until W1C.
• Include pending SBA starts in busy status.
• Make dmactive reset stop admission, drain accepted abstract/SBA work, reset DM state, then report inactive. Software must poll dmactive; writes during deactivation are ignored. A stretched old SBA ACK must return low before reuse. Ready-always backends can qualify ACK with request.

Scope

Core boundary changes apply to non-H, non-speculative in-order execution. H/OoO/speculative core paths retain their existing behavior. No board AXI/UIO/OpenOCD integration or trigger/step redesign is included.

This is not a full Debug v1.0 compliance upgrade; debugger-written dcsr.prv restoration remains an existing limitation. Deactivation waits for backends to complete rather than timing out and dropping ownership. Platform reset must also reset the backends.

Validation

• 74 identical paired cases: baseline 14 pass / 60 assertion failures, patched 74 pass; every baseline pass preserved. Twelve reset cases include the selected drain/admission policy, not standalone architectural-conformance claims.
• 34 additional direct-interface cases pass, including live RV32/RV64 cores with combinational and registered register files: 108 patched passes total.
• Covers memory-effect counts, held/pulsed halt, branch/compressed DPC, edited DPC, pending fetch, command ownership, delayed completions, stretched responses, reset/reactivation and existing JTAG/ebreak/trigger controls.
• Identical package analysis: 21 warnings and 11 infos on both versions. Eight configurations emit SystemVerilog; no synthesis or hardware timing claim.

Shared fixtures now activate/poll the DM and use bounded halt acknowledgement waits rather than assuming an in-flight microcoded instruction can stop within four/40 cycles.