feat(cache): add instruction-only L1 configurations

[murdoa]

Summary

Add HarborL1CacheConfig.instructionOnly(i) to represent an instruction cache without a data cache. Existing split/unified constructors, defaults and rendering remain unchanged.

General/unified constructors still require a non-null data configuration; instruction-only requires a non-null instruction configuration. An empty configuration cannot be created through these constructors merely by disabling assertions.

No cache-controller, refill-fault, dependency, board or timing changes.

API compatibility

HarborL1CacheConfig.d becomes nullable. Existing constructor calls remain valid, but consumers that dereference d must handle its absence. This is a source-level API change, not a transparent upgrade for those callers.

River's core, physical stage and emulator adaptations have been prepared and tested locally. The consumer PR needs a dependency revision containing both this API and the pending synchronous-tag/physical-capacity work; no local path override is intended for publication.

Validation

• Complete Harbor cache suite: 186 baseline passes → 188 patched passes, no failures/skips or lost passes.
• Analyzer clean on both trees.
• Three null arguments rejected in a standalone assertions-disabled run.
• Adapted River consumer: 98 paired control passes preserved, plus 20 instruction-only checks covering cached fetches, uncached data, faults, flushes and emulator behavior.
• Four legacy emitted-stage RTL profiles unchanged except generation time; two instruction-only Xilinx RTL simulations pass with no D-cache module emitted.

Consumer validation uses the exact local Harbor source. Coverage is limited to these suites and configurations, not the entire packages. No timing, area or FPGA-boot claim.