Caculator_designed_by_verilog_HDL

file_catalogs_structure:

main.v
$~~~~~~~$ ---divclk.v
$~~~~~~~$ ---v_ajxd.v
$~~~~~~~$ ---bind2bcd.v
$~~~~~~~$ ---v_disp1.v
$~~~~~~~$ ---beep.v

---

development environment

Verilog HDL vivado

---

LICENCE

GPL3.0

Author
$~~~~~~~$ ---Tsjinsins
$~~~~~~~$ ---Onion

关于

NameSpace: bigonion.cn
Origin: bigonion.cn/blog

Powered by md.bigonion.cn