syn the fork #2
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syn the fork #2
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* Added Xilinx 2019.2 toolset support * Enabled Vitis Runs * Updated XRT link for 2019.1 * Update ERRATA.md * Add errata that CL cannot connect shell generated clock directly to BUFG in CL. Co-authored-by: AWSkhanasif <khanasif@amazon.com>
* Added link to Xilinx AR# 73360 * Updated README to point to Vitis as the initial start point for new development
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