Update RELEASE_NOTES.md

RELEASE_NOTES.md

@@ -27,7 +27,7 @@
          *    3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)
 
 ## Release 1.4.4 (See [ERRATA](./ERRATA.md) for unsupported features)        
-* Fixed compile issues in Simulation while using  3rd party simulators (synopsys VCS, Cadence IES and Menor Questasim).
+* Fixed compile issues in simulation while using 3rd party simulators (synopsys VCS, Cadence IES and Mentor Questasim).
 
 ## Release 1.4.3 (See [ERRATA](./ERRATA.md) for unsupported features)
 * [DRAM Data Retention](hdk/docs/data_retention.md) - With DRAM data retention, developers can simply load a new AFI and continue using the data that is persistently kept in the DRAM attached to the FPGA, eliminating unnecessary data movements and greatly improving the overall application performance.