Merge branch 'espressif:master' into master

.gitlab/ci/host-test.yml

@@ -302,7 +302,6 @@ test_pytest_qemu:
       - "**/build*/*.bin"
     reports:
       junit: XUNIT_RESULT.xml
-  allow_failure: true # IDFCI-1752
   parallel:
     matrix:
       - IDF_TARGET: [esp32, esp32c3]

components/bootloader_support/src/esp32c5/bootloader_esp32c5.c

@@ -38,12 +38,10 @@
 #include "esp_efuse.h"
 #include "hal/mmu_hal.h"
 #include "hal/cache_hal.h"
-#include "hal/clk_tree_ll.h"
 #include "soc/lp_wdt_reg.h"
 #include "hal/efuse_hal.h"
 #include "hal/lpwdt_ll.h"
-#include "modem/modem_lpcon_reg.h"
-#include "modem/modem_syscon_reg.h"
+#include "hal/regi2c_ctrl_ll.h"
 
 static const char *TAG = "boot.esp32c5";
 
@@ -86,10 +84,9 @@ static void bootloader_super_wdt_auto_feed(void)
 
 static inline void bootloader_hardware_init(void)
 {
-    /* Enable analog i2c master clock */
-    SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
-    SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_FORCE_ON_REG, MODEM_LPCON_CLK_I2C_MST_FO); // TODO: IDF-8667 Remove this?
-    SET_PERI_REG_MASK(MODEM_SYSCON_CLK_CONF_REG, MODEM_SYSCON_CLK_I2C_MST_SEL_160M);
+    regi2c_ctrl_ll_master_enable_clock(true);
+    regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-8667 Remove this?
+    regi2c_ctrl_ll_master_configure_clock();
 }
 
 static inline void bootloader_ana_reset_config(void)

components/bootloader_support/src/esp32c6/bootloader_esp32c6.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -43,7 +43,7 @@
 #include "soc/lp_wdt_reg.h"
 #include "hal/efuse_hal.h"
 #include "hal/lpwdt_ll.h"
-#include "modem/modem_lpcon_reg.h"
+#include "hal/regi2c_ctrl_ll.h"
 
 static const char *TAG = "boot.esp32c6";
 
@@ -95,9 +95,8 @@ static inline void bootloader_hardware_init(void)
     esp_rom_spiflash_fix_dummylen(1, 1);
 #endif
 
-    /* Enable analog i2c master clock */
-    SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
-    SET_PERI_REG_MASK(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M);
+    regi2c_ctrl_ll_master_enable_clock(true);
+    regi2c_ctrl_ll_master_configure_clock();
 }
 
 static inline void bootloader_ana_reset_config(void)
@@ -167,7 +166,7 @@ esp_err_t bootloader_init(void)
     }
 #endif // !CONFIG_APP_BUILD_TYPE_RAM
 
-    // check whether a WDT reset happend
+    // check whether a WDT reset happened
     bootloader_check_wdt_reset();
     // config WDT
     bootloader_config_wdt();

components/bootloader_support/src/esp32c61/bootloader_esp32c61.c

@@ -43,6 +43,7 @@
 #include "soc/lp_wdt_reg.h"
 #include "hal/efuse_hal.h"
 #include "hal/lpwdt_ll.h"
+#include "hal/regi2c_ctrl_ll.h"
 
 static const char *TAG = "boot.esp32c61";
 
@@ -94,12 +95,9 @@ static inline void bootloader_hardware_init(void)
     esp_rom_spiflash_fix_dummylen(1, 1);
 #endif
 
-//TODO: [ESP32C61] IDF-9276
-#if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
-    ESP_EARLY_LOGW(TAG, "ESP32C61 attention: analog i2c master clock enable skipped!!!");
-#else
-    ESP_LOGW(TAG, "ESP32C61 attention: analog i2c master clock enable skipped!!!");
-#endif
+    regi2c_ctrl_ll_master_enable_clock(true);
+    regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this?
+    regi2c_ctrl_ll_master_configure_clock();
 }
 
 static inline void bootloader_ana_reset_config(void)

components/bootloader_support/src/esp32h2/bootloader_esp32h2.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -31,7 +31,6 @@
 #include "esp_private/regi2c_ctrl.h"
 #include "soc/regi2c_lp_bias.h"
 #include "soc/regi2c_bias.h"
-#include "modem/modem_lpcon_reg.h"
 #include "bootloader_console.h"
 #include "bootloader_flash_priv.h"
 #include "bootloader_soc.h"
@@ -43,7 +42,7 @@
 #include "soc/lp_wdt_reg.h"
 #include "soc/pmu_reg.h"
 #include "hal/efuse_hal.h"
-#include "modem/modem_lpcon_reg.h"
+#include "hal/regi2c_ctrl_ll.h"
 
 static const char *TAG = "boot.esp32h2";
 
@@ -89,8 +88,9 @@ static inline void bootloader_hardware_init(void)
     /* Disable RF pll by default */
     CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFPLL);
     SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_FORCE_RFPLL);
-    /* Enable analog i2c master clock */
-    SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
+
+    regi2c_ctrl_ll_master_enable_clock(true);
+    regi2c_ctrl_ll_master_configure_clock();
 }
 
 static inline void bootloader_ana_reset_config(void)
@@ -160,7 +160,7 @@ esp_err_t bootloader_init(void)
     }
 #endif // !CONFIG_APP_BUILD_TYPE_RAM
 
-    // check whether a WDT reset happend
+    // check whether a WDT reset happened
     bootloader_check_wdt_reset();
     // config WDT
     bootloader_config_wdt();

components/bootloader_support/src/esp32p4/bootloader_esp32p4.c

@@ -48,6 +48,7 @@
 #include "soc/regi2c_cpll.h"
 #include "soc/regi2c_bias.h"
 #include "esp_private/periph_ctrl.h"
+#include "hal/regi2c_ctrl_ll.h"
 
 static const char *TAG = "boot.esp32p4";
 
@@ -92,8 +93,10 @@ static void bootloader_super_wdt_auto_feed(void)
 
 static inline void bootloader_hardware_init(void)
 {
-    int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused));
-    // regi2c is enabled by default on ESP32P4, do nothing
+    int __DECLARE_RCC_RC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors/warnings about __DECLARE_RCC_RC_ATOMIC_ENV
+    regi2c_ctrl_ll_master_enable_clock(true);
+    regi2c_ctrl_ll_master_configure_clock();
+
     unsigned chip_version = efuse_hal_chip_revision();
     if (!ESP_CHIP_REV_ABOVE(chip_version, 1)) {
         // On ESP32P4 ECO0, the default (power on reset) CPLL and SPLL frequencies are very high, lower them to avoid bias may not be enough in bootloader
@@ -106,6 +109,7 @@ static inline void bootloader_hardware_init(void)
     REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 10);
 
     // IDF-10019 TODO: This is temporarily for ESP32P4-ECO0, please remove it when eco0 is not widly used.
+    int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused));
     if (likely(ESP_CHIP_REV_ABOVE(chip_version, 1))) {
         spimem_flash_ll_select_clk_source(0, FLASH_CLK_SRC_SPLL);
         spimem_ctrlr_ll_set_core_clock(0, 6);

components/bt/CMakeLists.txt

@@ -4,29 +4,17 @@ if(${target} STREQUAL "linux")
     return() # This component is not supported by the POSIX/Linux simulator
 endif()
 
+if(CONFIG_IDF_TARGET_ESP32S3)
+    set(target_name "esp32c3")
+else()
+    set(target_name "${idf_target}")
+endif()
+
 # API headers that are used in the docs are also compiled
 # even if CONFIG_BT_ENABLED=n as long as CONFIG_IDF_DOC_BUILD=y
 
-if(CONFIG_IDF_TARGET_ESP32)
-    set(target_specific_include_dirs include/esp32/include)
-
-elseif(CONFIG_IDF_TARGET_ESP32C3)
-    set(target_specific_include_dirs include/esp32c3/include)
-
-elseif(CONFIG_IDF_TARGET_ESP32S3)
-    set(target_specific_include_dirs include/esp32c3/include)
-
-elseif(CONFIG_IDF_TARGET_ESP32C2)
-    set(target_specific_include_dirs include/esp32c2/include)
-
-elseif(CONFIG_IDF_TARGET_ESP32C6)
-    set(target_specific_include_dirs include/esp32c6/include)
-
-elseif(CONFIG_IDF_TARGET_ESP32H2)
-    set(target_specific_include_dirs include/esp32h2/include)
-
-elseif(CONFIG_IDF_TARGET_ESP32C5)
-    set(target_specific_include_dirs include/esp32c5/include)
+if(CONFIG_SOC_BT_SUPPORTED)
+    set(target_specific_include_dirs include/${target_name}/include)
 endif()
 
 set(common_include_dirs
@@ -76,34 +64,19 @@ if(CONFIG_BT_ENABLED)
     set(include_dirs "")
     set(ldscripts "linker_common.lf")
     if(CONFIG_BT_CONTROLLER_ENABLED)
+        list(APPEND srcs "controller/${target_name}/bt.c")
+
         if(CONFIG_IDF_TARGET_ESP32)
-            list(APPEND srcs "controller/esp32/bt.c"
-                             "controller/esp32/hli_api.c"
+            list(APPEND srcs "controller/esp32/hli_api.c"
                              "controller/esp32/hli_vectors.S")
             list(APPEND ldscripts "linker_rw_bt_controller.lf")
-
         elseif(CONFIG_IDF_TARGET_ESP32C3)
-            list(APPEND srcs "controller/esp32c3/bt.c")
             list(APPEND ldscripts "linker_rw_bt_controller.lf")
-
         elseif(CONFIG_IDF_TARGET_ESP32S3)
-            list(APPEND srcs "controller/esp32c3/bt.c")
             list(APPEND ldscripts "linker_rw_bt_controller.lf")
-
         elseif(CONFIG_IDF_TARGET_ESP32C2)
-            list(APPEND srcs "controller/esp32c2/bt.c")
             set(ldscripts "linker_esp32c2.lf")
-
-        elseif(CONFIG_IDF_TARGET_ESP32C6)
-            list(APPEND srcs "controller/esp32c6/bt.c")
-            list(APPEND ldscripts "linker_esp_ble_controller.lf")
-
-        elseif(CONFIG_IDF_TARGET_ESP32H2)
-            list(APPEND srcs "controller/esp32h2/bt.c")
-            list(APPEND ldscripts "linker_esp_ble_controller.lf")
-
-        elseif(CONFIG_IDF_TARGET_ESP32C5)
-            list(APPEND srcs "controller/esp32c5/bt.c")
+        else()
             list(APPEND ldscripts "linker_esp_ble_controller.lf")
         endif()
 
@@ -870,7 +843,7 @@ if(CONFIG_BT_ENABLED)
                 "${CMAKE_CURRENT_LIST_DIR}/controller/lib_esp32c3_family/esp32s3")
         target_link_libraries(${COMPONENT_LIB} PUBLIC btdm_app)
     elseif(CONFIG_BT_CONTROLLER_ENABLED)
-        add_prebuilt_library(libble_app "controller/lib_${target}/${target}-bt-lib/libble_app.a")
+        add_prebuilt_library(libble_app "controller/lib_${target_name}/${target_name}-bt-lib/libble_app.a")
         target_link_libraries(${COMPONENT_LIB} PRIVATE libble_app)
     endif()
 

components/bt/controller/esp32/Kconfig.in

@@ -67,7 +67,7 @@ config BTDM_CTRL_BR_EDR_SCO_DATA_PATH_EFF
     default 0
 
 menuconfig BTDM_CTRL_PCM_ROLE_EDGE_CONFIG
-    bool "PCM Signal Config (Role and Polar)"
+    bool "PCM Signal Configurations: Role, Polar and Channel Mode(Stereo/Mono)"
     depends on BTDM_CTRL_BR_EDR_SCO_DATA_PATH_PCM
     default y
 
@@ -95,6 +95,37 @@ choice BTDM_CTRL_PCM_POLAR
         bool "Rising Edge"
 endchoice
 
+choice BTDM_CTRL_PCM_FSYNCSHP
+    prompt "Channel Mode(Stereo/Mono)"
+    depends on BTDM_CTRL_PCM_ROLE_EDGE_CONFIG
+    default BTDM_CTRL_PCM_FSYNCSHP_STEREO_MODE
+    help
+        PCM frame synchronization signal shape can be configured as Stereo Mode or Mono Mode.
+        (There are detailed instructions under the path examples/bluetooth/bluedroid/classic_bt/hfp_ag/README.md)
+
+    config BTDM_CTRL_PCM_FSYNCSHP_STEREO_MODE
+        bool "Stereo Mode"
+        help
+            Stereo Mode(Dual channel): FSYNC and DOUT signals both change simultaneously on the edge of CLK.
+            The FSYNC signal continues until the end of the current channel-data transmission.
+            (There is a waveform graph under the path examples/bluetooth/bluedroid/classic_bt/hfp_ag/image)
+
+    config BTDM_CTRL_PCM_FSYNCSHP_MONO_MODE_LF
+        bool "Mono Mode 1"
+        help
+            Mono Mode 1(Single channel): FSYNC signal starts to change a CLK clock cycle earlier than the DOUT signal.
+            The FSYNC signal continues for one extra CLK clock cycle.
+            (There is a waveform graph under the path examples/bluetooth/bluedroid/classic_bt/hfp_ag/image)
+
+    config BTDM_CTRL_PCM_FSYNCSHP_MONO_MODE_FF
+        bool "Mono Mode 2"
+        help
+            Mono Mode 2(Single channel): FSYNC and DOUT signals both change simultaneously on the edge of CLK.
+            The FSYNC signal continues for one extra CLK clock cycle.
+            (There is a waveform graph under the path examples/bluetooth/bluedroid/classic_bt/hfp_ag/image)
+
+endchoice
+
 config BTDM_CTRL_PCM_ROLE_EFF
     int
     default 0 if BTDM_CTRL_PCM_ROLE_MASTER
@@ -107,6 +138,13 @@ config BTDM_CTRL_PCM_POLAR_EFF
     default 1 if BTDM_CTRL_PCM_POLAR_RISING_EDGE
     default 0
 
+config BTDM_CTRL_PCM_FSYNCSHP_EFF
+    int
+    default 0 if BTDM_CTRL_PCM_FSYNCSHP_STEREO_MODE
+    default 1 if BTDM_CTRL_PCM_FSYNCSHP_MONO_MODE_LF
+    default 2 if BTDM_CTRL_PCM_FSYNCSHP_MONO_MODE_FF
+    default 0
+
 config BTDM_CTRL_AUTO_LATENCY
     bool "Auto latency"
     depends on BTDM_CTRL_MODE_BTDM

components/bt/controller/esp32c5/bt.c

@@ -303,34 +303,34 @@ static int esp_intr_free_wrapper(void **ret_handle)
 void esp_bt_rtc_slow_clk_select(uint8_t slow_clk_src)
 {
     /* Select slow clock source for BT momdule */
-    // switch (slow_clk_src) {
-    //     case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
-    //         ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using main XTAL as clock source");
-    //         uint32_t chip_version = efuse_hal_chip_revision();
-    //         if (chip_version == 0) {
-    //             modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (400 - 1));
-    //         } else{
-    //             modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (5 - 1));
-    //         }
-    //         break;
-    //     case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
-    //         ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using 136 kHz RC as clock source, can only run legacy ADV or SCAN due to low clock accuracy!");
-    //         modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (5 - 1));
-    //         break;
-    //     case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
-    //         ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using external 32.768 kHz XTAL as clock source");
-    //         modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (1 - 1));
-    //         break;
-    //     case MODEM_CLOCK_LPCLK_SRC_RC32K:
-    //         ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using 32 kHz RC as clock source, can only run legacy ADV or SCAN due to low clock accuracy!");
-    //         modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (1 - 1));
-    //         break;
-    //     case MODEM_CLOCK_LPCLK_SRC_EXT32K:
-    //         ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using 32 kHz oscillator as clock source, can only run legacy ADV or SCAN due to low clock accuracy!");
-    //         modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (1 - 1));
-    //         break;
-    //     default:
-    // }
+    switch (slow_clk_src) {
+        case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
+            ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using main XTAL as clock source");
+            uint32_t chip_version = efuse_hal_chip_revision();
+            if (chip_version == 0) {
+                modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (400 - 1));
+            } else{
+                modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (5 - 1));
+            }
+            break;
+        case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
+            ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using 136 kHz RC as clock source, can only run legacy ADV or SCAN due to low clock accuracy!");
+            modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (5 - 1));
+            break;
+        case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
+            ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using external 32.768 kHz XTAL as clock source");
+            modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (1 - 1));
+            break;
+        case MODEM_CLOCK_LPCLK_SRC_RC32K:
+            ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using 32 kHz RC as clock source, can only run legacy ADV or SCAN due to low clock accuracy!");
+            modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (1 - 1));
+            break;
+        case MODEM_CLOCK_LPCLK_SRC_EXT32K:
+            ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using 32 kHz oscillator as clock source, can only run legacy ADV or SCAN due to low clock accuracy!");
+            modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (1 - 1));
+            break;
+        default:
+    }
 }
 
 IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)