Add exact MoVA serving to xLLM

[akhauriyash]

What changed

• Adds native MoVA attention for the xLLM model family.
• Packs Q/K/gate projections and output-shards routed value experts for TP serving.
• Reuses ordinary paged K/routed-V caching, including prefix caching and chunked prefill.
• Preserves selection-only FP32 router-bias semantics, grouped RMSNorm, interleaved RoPE, and the softplus attention gate.
• Adds fail-fast validation for unsupported phase-one configurations.

Why

MoVA RL rollouts need a native SGLang implementation with CUDA-graph-safe kernels and a stable weight-loading contract. The existing xLLM vLLM bridge is a useful correctness reference but is not the production SGLang path.

Validation

• 25 focused tests covering router/value math, TP sharding/loading, mappings, RoPE, norms, CUDA graph replay, and fullgraph compile.
• Real 36B TP8 BF16 acceptance: load, cached decode, concurrent batching, radix-prefix reuse, and chunked prefill.
• A 16-prompt HF-vs-SGLang parity corpus and corrected real-model production rerun are in progress; keep this draft until those gates are recorded.