Pedestal Alignment

[rodr1001]

Developing an algorithm to determine best DACb and TRIM_INV values for each channel that will result in an ADC value closest to the median ADC value with default settings. This is the first step of pedestal alignment as outlined in the CMS HGCROC Tuning Procedure (linked in the pflib wiki)

[erik-wallin]

Thanks for looking into this! There seems to be some different recipes for how to do the pedestal alignment.

• Some minor details about this can be found in José's thesis, especially sections 4.3.3 and 4.5.2: https://theses.hal.science/tel-04694842v1 (Really recommend reading whole chapters of this text)

• There are some details in this talk: https://indico.fnal.gov/event/69566/contributions/316163/attachments/187982/259296/TB_QC_Mekhala_UMD_10July2024.pdf

• The shaper section of the data sheet talks about this, although I don't understand it.

And there is a recipe we got from some CMS colleagues at DESY, before the 2022 testbeam.

Recipe at the testbeam and v2 teststand

We had a student in Lund a couple of years ago, Lisa, who attempted to automate this on version 2 of the chip.

Lisa's code can be found here: 7856d57

I think it's worth reading through, because she spent a lot of time trying to get a feel for this.

To summarize it:

1. Set gain_conv to 0 to not allow any signal into the pre-amp. The reasoning is that we first align all the pedestals using the shaper first, then we connect it to the outside world in a later stage.
2. Find a good combination of inv_vref and noinv_vref
3. Increase individual channels upwards with ref_dac_inv
4. Set gain_conv to physics mode (probably gain_conv = 4) and let signals in again.
5. Align channels with dacb and sign_dacb

This method worked well for 99% of channels, but there were always a few that had to be manually tuned by hand. But quite reliably, it managed to trim the pedestal to a value of 100 ADC +- 10. I wonder how far down we can get. 80? 50 even?

Notes

Things feel different when you connect the SiPMs and bias them. You get detector capacitance, leakage current and so on. If you have the possibility, do the pedestal alignment on connected and biased channels.

When choosing a combination of inv_vref and noinv_vref it sort of feels like both parameters do the same thing, just shifting the pedestal up or down. But in the v2 chip there we combinations that were not functioning. Let's map out the parameter space of these two parameters, and see what a well-behaved working region is.

Dacb is a parameter to correct for leakage current. It just happens to conveniently change the pedestal as well. But if you turn up dacb too high, you can accidentally start saturating the pre-amp early. Let's be mindful of also looking at whether anything happens to the pulse shapes when we change different parameters! Also in the v2 chip, there were ranges of dacb that were not functioning, and sign_dacb was not very well behaved.

Ref_dac_inv (or whatever it's called in the v3 chip) was always easy to control in comparison to dacb, never saw any unintended consequences from changing that.

[rodr1001]

did an initial 10k event pedestal run with trim_inv, dacb & sign_dac set to 0 (default settings).

here's that default, for reference

for each channel, found the median ADC value. then for each link, found the median of all the channels (so link_0_median, link_1_median)

then did a pedestal run with trim_inv = 63 (all other settings remained the same)
again, finding the median ADC for each channel and use these values and the original values with numpy.interpolate to find the value of trim_inv that gets us closest to the median.

this step works only for those with an initial ADC value lesser than the link median.

then another pedestal run is done, with sign_dac = 1, dacb =31 and trim_inv = 0. then we can use the median for each channel and the original values with numpy.interpolate again to find the dacb value that brings us closest to the link median.

these are the results from this so far

i've done all of this analysis in python. hoping to rewrite this in c++ so this part of the pedestal leveling can all be done in pftool without the intermediary steps (wrangling csv files)

this is all done following this talk https://indico.fnal.gov/event/69566/contributions/316163/attachments/187982/259296/TB_QC_Mekhala_UMD_10July2024.pdf
where each link is leveled first with the trim_inv and dacb scans. moving forward i'll be looking at inv_vref and noinv_vref

[rodr1001]

the next step was to manipulate inv_vref and noinv_vref in such a way as to reduce the median ADC count to 50 (± 1). The default setting for both links are inv_vref = 416 and noinv_vref = 836.

Found relatively decent success with manipulating inv_vref to obtain a lower median value, however, not at the desired value.

This did not use the method detailed above, which may explain some issues. Instead GEN_SCAN was done with some sample inv_vref values (using channel 0 and channel 71 as representative for link 0 and link 1 respectively). From that data, I tried interpolating to a value that would give an ADC count of 50 and then did a fine tuning run of GEN_SCAN with all possible inv_vref values between 400 and 600. There were multiple values of inv_vref that gave 49 or 51 (I did not see any return 50 exact, unsure why). I used the mean of these values and did a pedestal run to test these new inv_vref values.

For link 0, I used an inv_vref value of 520 and link 1, an inv_vref value of 512.
These were able to shift the median values down to 60 and 68.5 for link 0 and link 1 respectively.

[OwenCole04]

I also started taking a look at using inv_vref to reduce median ADC count and align the two links. I started by running the pedestal leveling algorithm to get each link's pedestals leveled. With noinv_vref held at its default value, I then took a scan of inv_vref, scanning from inv_vref = 0 to 600 in increments of 20. I then chose a channel from each link and applied a linear fit within the linear regime for inv_vref vs adc (I defined it as between .1 and .85 of the max adc in my python script). Using the regression, I set a target ADC and found the optimal inv_vref value for each link to attain the target ADC. With a target ADC of 50, I got inv_vref = 559 and 530 for links 0 and 1 respectively, and with a pedestal run was able to attain a median adc count of 50 and 51 for links 0 and 1 respectively.

[tomeichlersmith]

Closing in favor of #222