minor adjustment on readme and documentation

README.rst

@@ -69,6 +69,7 @@ computation.
 
        @sv()
        def min(self):
+           # call the numpy function
            return np.min(self.__array)
 
        @sv(return_type=DataType.Bit)
@@ -97,6 +98,8 @@ Now we can use the class directly with the SystemVerilog binding:
     a.add_element(1);
     assert(a.exists(1));
     assert(!a.exists(2));
+    // numpy under the hood!
+    assert(a.min() == 1);
 
 
 .. _pybind11: https://github.com/pybind/pybind11

docs/advanced/internal.rst

@@ -3,7 +3,9 @@
 How pysv works
 ==============
 
-pysv relies heavily on pybind11 to interface with Python interpreter.
+pysv relies heavily on pybind11 to interface with Python interpreter. It is done via
+embedding the Python interpreter inside the shared library. You can find more details
+on `pybind11's documentation`_.
 
 
 Function code generation
@@ -129,10 +131,19 @@ Here is an example to see generated SystemVerilog class definition
     endclass
     endpackage
 
+DPI functions are in the form of
+
+.. code-block:: SystemVerilog
+
+  import "DPI-C" function chandle Foo_pysv_init();
+
+Python types are converted into SystemVerilog types based on auto detection or user-provided
+``DataType``.  
 
 Notice that the class methods is flattened into normal function where the first
 argument is the C pointer. Each generated class will hold a pointer to its
 corresponding Python class object.
 
 
 .. _DPI: https://en.wikipedia.org/wiki/SystemVerilog_DPI
+.. _pybind11's documentation: https://pybind11.readthedocs.io/en/stable/advanced/embedding.html

docs/advanced/oop.rst

@@ -37,7 +37,7 @@ export the methods decorated with ``@sv``.
   ``@sv`` decorator since pysv will generate default constructor automatically. Nonetheless,
   it doesn't hurt to decorate the constructor.
 
-To use it in the SystemVerilog, first, we generate the SystemVerilog binding
+To use it in the SystemVerilog, we need to first generate the SystemVerilog binding
 
 .. code-block:: Python
 
@@ -107,7 +107,7 @@ class generated:
 
 Notice that every SystemVerilog wrapper class is inherited from the base class
 ``PySVObject``, which has an C pointer to the actual Python object. To allow
-wrapper objects being created without the pointer only, we added additional
+wrapper objects being created with the pointer only, we added additional
 argument to the constructor, since SystemVerilog does not support function
 overloading.
 
@@ -117,11 +117,11 @@ function is generated as follows, with proper function signature.
 .. code-block:: SystemVerilog
 
   function int foo_bar(input Foo foo,
-                      input int num);
+                       input int num);
     return foo_bar_(foo.pysv_ptr, num);
   endfunction
 
-For cases where you need duck-type the Python objects, you can set the argument
+For cases where you need to duck-type the Python objects, you can set the argument
 or type to ``DataType.Object``. With that, ``PySVObject`` type will be used in
 the signature, which avoids illegal downcast in SystemVerilog.
 

docs/advanced/systemverilog.rst

@@ -3,7 +3,7 @@
 Use pysv with SystemVerilog
 ===========================
 
-This sections will cover usages with common SystemVerilog simulator.
+This sections will cover usages with common SystemVerilog simulators.
 Too see how to generate SystemVerilog binding with classes,
 please refer to :ref:`sv-binding` and :doc:`oop`.
 
@@ -28,8 +28,8 @@ VCS follows the exact same flag as Xcelium:
 
   vcs design1.sv design2.sv pysv_pkg.sv top.sv -sverilog -sv_lib build/libpysv.so
 
-Notice that we need additional `-sverilog` to let the parser switch to SystemVerilog
-mode.
+Notice that we need the additional `-sverilog` flag to let the parser switch to
+SystemVerilog mode.
 
 Mentor Questa®
 --------------

docs/advanced/verilator.rst

@@ -12,9 +12,11 @@ Too see how to generate C++ binding with classes, please refer to
 
   .. code-block::
     
-    verilator --cc design1.sv design2.sv top.cc pysv_cxx.hh libpysv.so
+    verilator --cc design1.sv design2.sv top.cc libpysv.so
 
-2. Make sure ``libpysv.so`` is in your ``LD_LIBRARY_PATH`` when you run
+2. Copy the CXX binding file to proper places so your test bench code can include it.
+
+3. Make sure ``libpysv.so`` is in your ``LD_LIBRARY_PATH`` when you run
    the test bench binary, e.g.
 
   .. code-block::

docs/basics.rst

@@ -2,7 +2,7 @@
 
 Basic usages
 ============
-This sections demonstrates the basic features of pysv.
+This section demonstrates the basic features of pysv.
 
 Hello World!
 ------------
@@ -50,7 +50,8 @@ Function arguments and return types
 -----------------------------------
 By default, if a function argument type is not specified, pysv will assume it is of
 ``DataType.Int`` type (``int32_t`` in C).
-To specify the argument type, we can add the types to the function decorator.
+To specify the argument type, we can add the types to the function decorator with given
+argument name.
 
 .. code-block:: Python
 
@@ -174,9 +175,9 @@ There are some optional arguments provided with default values:
   is ``True``.
 - ``filename``: if provided, pysv will write the binding code to the specified
   filename.
-- ``include_implementation``: if set ``True``, the actual C++ implemented will be
+- ``include_implementation``: if set to ``True``, the actual C++ implemented will be
   generated as well. Only for debugging, since the functions are not declared as
-  ``inline`` and will verily trigger linker error.
+  ``inline`` and will likely trigger a linker error.
 
 .. note::
 
@@ -231,6 +232,6 @@ simulation.
 
 .. warning::
 
-  For a small-scale simulation, especially with Verilator or no foreign modules are imported
+  For a small-scale simulation, especially with Verilator or no foreign modules are imported,
   ending simulation without calling ``pysv_finalize()`` will be fine in most cases. However,
   it is the best practice to call it at the end of simulation.

docs/install.rst

@@ -39,7 +39,7 @@ SystemVerilog simulators
 pysv is designed to be simulator agonistic: it can work with virtually any
 simulator that supports DPI function calls. Since pysv generates C++ code,
 it naturally supports Verilator. Here is a list of simulators that pysv has
-been tested one
+been tested on:
 
 - Cadence® Xcelium™
 - Synopsys VCS®