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A fast usermode x86 and x86-64 emulator for Arm64 Linux
Patching and hooking the Linux kernel with only a stripped Linux kernel image.
Microcode Updates for the USENIX 2017 paper: Reverse Engineering x86 Processor Microcode
Embedded web server, with TCP/IP network stack, MQTT and Websocket
3-wide superscalar, out-of-order RISC-V processor (RV32IM subset) in System Verilog, demonstrating key Instruction-Level Parallelism
Trust Domain Extensions (TDX) is introducing new, architectural elements to help deploy hardware-isolated, virtual machines (VMs) called trust domains (TDs). Intel TDX is designed to isolate VMs fr…
A research kernel and hypervisor attempting to get fully deterministic emulation with minimum performance cost
Reference setup for Linux kernel development in VSCode
Summary of bugs in Xuantie C9XX core design. include C906/C908/C910/C920
A tool for creating and running Linux containers using lightweight virtual machines on a Mac. It is written in Swift, and optimized for Apple silicon.
A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS
A powerful and user-friendly binary analysis platform!
🚀🚀 「大模型」2小时完全从0训练26M的小参数GPT！🌏 Train a 26M-parameter GPT from scratch in just 2h!
Assured confidential execution (ACE) implements VM-based trusted execution environment (TEE) for embedded RISC-V systems with focus on a formally verified and auditable firmware.
Group administration repository for Tech: Microarchitecture Side-Channel Resistant Instruction Spans (uSCR-IS)
devmem2 - simple program to read/write from/to any location in memory.
JetBrains Maple Mono: The free and open-source font fused with JetBrains Mono & Maple Mono
Patch your macOS kernel to enable support for the high-resolution timers on M1
A collection of links related to Linux kernel security and exploitation
cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
This upload contains the artifacts for the paper "SLAP: Data Speculation Attacks via Load Address Prediction on Apple Silicon", to appear at the 2025 IEEE Symposium on Security and Privacy.
A Fast, Low-Overhead On-chip Network
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Chisel RISC-V Vector 1.0 Implementation
