Added WeMos D1 Mini module

[Duckle29]

Added a module for the WeMos D1 Mini. The large crtyd is to allow for a USB cable to be inserted into the wemos

Thanks for creating a pull request to contribute to the KiCad libraries! To speed up integration of your PR, please check the following items:

Dimensions of the board This is the best I could find.
Symbol PR KiCad/kicad-symbols#727

• Check the output of the Travis automated check scripts - fix any errors as required

[Duckle29]

It now looks like this:

[herostrat]

Hey Duckle29,

some questions/things:

• why is the CtrYd extending so far down
• why did you call the reference on the Silk A1 and not Ref**?
• why is the CtrYd at the top not the same distance from the Silk than left and right?
• the middle point is not in the center but at Pin 1, I think it should be in the middle of the whole device
• I think the name is written WEMOS not WeMos, at least thats the way the spell it everywhere

[Duckle29]

@herostrat Hey :)

• I thought I commented on it, but clearly didn't. the long CtrYd is to allow for a USB plug to be inserted
• Probably a mistake from editing the module from within a design, will fix that
• That is a mistake
• Will do. I was following PTH part design rules :)
• Hmm odd. I swear it was WeMos on their own website when I was making this. Maybe I needed more coffee. Will fix that as well :)

[herostrat]

Hey, thanks for the update

Just a heads-up, I am no maintainer so take everything with a grain of salt.
Its just to help speed up reviewing and pointing out obvious stuff.

For the name, sometimes its:

But on the Github profile, their website and the shop and on some other hw revisions its all caps.

I don't know if they are inconsitent, if they changed it or whatever.
I guess I would go with WEMOS, but it's not up to me to decide.

About the PTH design rules, I could be wrong with my statement.
What do mean with it?
I only know about the center of the package, not centered around a specific pin.

One other thing I thought about.
Wouldn't it be interesting to also add a general template for a WEMOS/WeMoS D1 mini shield?

Thanks for updating :)

[poeschlr]

@herostrat wrote:

Just a heads-up, I am no maintainer so take everything with a grain of salt.

You seem to be quite interested in reviewing the work of others. So far your suggestions where not really wrong. (Some rules are not even known to us maintainers at every point in time. So even we make mistakes sometimes.) And regarding the "I am not a maintainer" comment: I can change that ;)

---

Regarding the point about the center:
For through hole components pin 1 should be at the origin. (So @Duckle29 has it correct.) This is one of the things our test scripts do check. (So if it would be wrong there would be a report)

---

Travis does however report that the reference is set to the wrong value. (looks like you started the footprint editor from within a pcb as it still has the reference A1. Change that to Ref** as suggested by our test script.)

[herostrat]

@poeschlr

Just a heads-up, I am no maintainer so take everything with a grain of salt.

You seem to be quite interested in reviewing the work of others. So far your suggestions where not really wrong. (Some rules are not even known to us maintainers at every point in time. So even we make mistakes sometimes.) And regarding the "I am not a maintainer" comment: I can change that ;)

That's very nice for you to say.
Let me come back to this if I think I am familiar enough with the rules and workflow.
Until than I just try to help out and learn stuff.
Coming from Eagle (because I had) and being "allowed" to switch to KiCad (or better convincing others) I love a community driven library so much.
It is a lot of work for few people but especially for novice or layman users interested in EE it is just awesome.

Regarding the point about the center:
For through hole components pin 1 should be at the origin. (So @Duckle29 has it correct.) This is one of the things our test scripts do check. (So if it would be wrong there would be a report)

That I didn't know.
Probably because I only did SMD devices since I started using KiCad.

[Duckle29]

I don't know why this was a closed. Probably because I force merged my local branch to clean up some mess

[Duckle29]

Footprint now looks like this:

with the 3D models looking like this:

I decided to not duplicate headers and sockets, as I felt like this was unnecessary, but that does mean I'm including multiple 3D files, and translating and rotating some. I was wondering what your opinion was on this, as I think this is the best solution to not redo 3D-models and waste space.

Relevant 3D model PR

[Duckle29]

@poeschlr Hey I just wanted to give a heads-up that I got back to this after leaving it for quite a while :)

[Misca1234]

@Duckle29
I am somewhat sceptical to include a crtyrd to make room for a usb dongle.
The fp should reflect the component itself, not any extra accessories it might need.
Also, the usb connector might come in different shapes and sizes so it "difficulty" to get this area
right. If the module is places in pins, the usb dongle will not occupy "space on the pcb" anyway.

I suggest you skip the reserved area for the usb connector

I am also somewhat sceptical to that you place the module already on those
pin headers, there might be cases where you solder the module directly onto the PCB

"https://c1.staticflickr.com/1/734/31400410271_f278b087db_z.jpg"
Seems to be right, on
https://wiki.wemos.cc/products:d1:d1_mini_lite
It says
Length 34.2mm
Width 25.6mm

If you want to absolutely sure you could send an email to wemos and ask them
about the put dimensions and also their recommended land patter for the module.
It might be so that they want a much larger keep out area for the antenna.
(there might be cases where the module is directly soldered onto a PCB without any distance)

@herostrat
If you look on this image (for this particular module)
https://wiki.wemos.cc/_media/products:d1:lite_v1.0.0_2_16x9.jpg
They use WEMOS

[Duckle29]

Hey there, thanks for taking a look.
http://kicad-pcb.org/libraries/klc/F5.3/ < if you look at number 6 in that list, it would suggest that connectors would need a crtyrd that allows for the mating connector to be plugged in. Reading it again, it is clear that it refers to just connectors, but I don't know what the "connector on a module" rule would be.

I agree that there's a lot of different USB cables, but a lot of them should fit the crtyrd I have put into this foot-print. I am not a huge fan of how it looks though, and would like to see an official "modules" section added to the KLC, that deals with these sorts of questions :)

As for dimensions, I have several different boards, both official from the manufacturer, and a lot of other boards from eBay and ali-express, they all fit the layout here.
As it often is with boards like these, the pin-spacing is in multiples of 0.1" and they use 0.1" pitch headers, as this is breadboard friendly. In this case, it's 0.9" between the rows.
I have also had a few different PCBs made with this footprint already, and the silk-screen aligns perfectly with the modules, so it seems to be spot on.

As for the keep-out, I mentioned that the most common of these boards, use the ESP8266MOD module. (mentioned that on the 3D model PR)

Because of this, I can see what keep-out they have used themselves, directly under the antenna of the ESP8266MOD, and this is the same keep-out I have further put in my footprint.

[Misca1234]

http://kicad-pcb.org/libraries/klc/F5.3/
if you look at number 6 in that list, it would suggest that connectors would need a
crtyrd that allows for the mating connector to be plugged in.

I am not sure this is the same use case as for your module.

About the clearance of the antenna, from what I can see the radio module is ESP8285, which in turn means espressif and here is their recommended land patterns for their modules regarding the antenna
https://www.espressif.com/sites/default/files/documentation/esp-wroom-02_pcb_design_and_module_placement_guide_0.pdf

They do have an option6 with no clearance area but all the others have 5 mm
Now, these options, except 1, talks about mounting the module on the pcb.
In your contribution you assume the module should be mounted on pin connectors,
are you sure you want to "restrict" your module to this.

[Duckle29]

Ahh I see what you mean with clearance.

Because of how the boards are made, they are actually already 10mm wider than the antenna (5mm on each side) so this is already implemented.

As for the crtyrd, I'm not sure either. I'd very much like a verdict on it, or maybe a module-specific section in the KLC :)

[herostrat]

I think the CrtYd should not include the connector, because it is a completely arbitrary size.

In other modules of the library there is also no CrtYd for them.
See for example:

@Misca1234 I also think WEMOS is the way to go :)

[Duckle29]

Okay, thanks for clearing that up. I wasn't a huge fan of it either, as it looked wonky and made the PCB layout a bit messy.

[Duckle29]

It now looks like this:

[herostrat]

Nice, thank you very much.
I think this is ok.

And you mentioning that it already worked in reallife is also a good indicator :)

[Misca1234]

It is a tricky module.

Also, are you sure that it is the mini and not mini lite you are doing ?
https://wiki.wemos.cc/products:d1:d1_mini_lite
https://wiki.wemos.cc/products:d1:d1_mini

If it is the mini lite, you need to change the name of the file to include lite (so others can make the mini one without name clashing)
If it is the mini, you need the holes in the corners

MiniLite:
If it is mini lite you should make the whole area beneath the module to keep out area so
it can be safetly soldered directly on the pcb.
On the other hand the pins to the usb connector will prevent it to be soldered directly on the PCB which means that you need to make holes for them (you need a better drawing from WEMOS)

Mini:
Because of the components on the back side, it can not be mounted directly on a pcb but need a distance pin connector which in turns mean that many components can actually be mounted under it, depending on the height of the distance pins.

Which in turn would imply that the F.Fab and F.CrtYrd should just enclose the pin holes and make it possible to use the area beneath the module (keep the keep out area) ?

What do you think about that ?

[Duckle29]

I agree that it looks more like the lite board. and that it should be named as such. What had me confused is that the boards I have all have 4MB of flash, which is mini should have, however, I think that flash-size is more relevant for software.
Since this is a footprint, I think it should be named light, as it is physically identical to the light version.

[Duckle29]

As for the holes and such. I do not agree that I should make cutouts for the USB plug or other such things, nor do I agree that the entire area underneath should be keep-out.

If a designer wishes to place the device flush to the PCB, then that designer should know not to put any parts underneath, additionally, most boards bought on eBay and similar, have just the module on top, and then a lot of components on the bottom, meaning you run into the same issues as you would with the mini. The modules are meant to be plugged into headers.

[herostrat]

Just asking out of curiosity: how would you solder the d1 mini lite to the pcb directly?
For use-cases like this I only know of castellated mounting holes.

Imho it is meant to be used with pin-headers or even stack-able with a pin-socket on the pcb an headers on the wemos. At least I have only seen implementation like this (including one of mine)

[Duckle29]

A note on silk following the contour. It's a visual guide to properly orient the wemos when inserting into PCB, something I've had to use quite a few times now :)

[Misca1234]

Ok, but the F.Fab should follow the contour of the component

[Misca1234]

@Duckle29
I have modified your FP,
rounded corners, placed F.Silk outside F.Fab, modified pin 1 marker, added datasheet links
check it out, say what you think

(module WEMOS_D1_mini_light (layer F.Cu) (tedit 5BB78BEF)
(descr "16-pin module, collum spacing 22.86 mm (900 mils), https://wiki.wemos.cc/products:d1:d1_mini, https://c1.staticflickr.com/1/734/31400410271_f278b087db_z.jpg")
(tags "ESP8266 WiFi microcontroller")
(fp_text reference REF** (at 22 27) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value WEMOS_D1_mini_light (at 11.7 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.04 26.12) (end 24.36 26.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.5 19.22) (end -1.5 -6.21) (layer F.SilkS) (width 0.12))
(fp_line (start 24.36 26.12) (end 24.36 -6.21) (layer F.SilkS) (width 0.12))
(fp_line (start 22.24 -8.34) (end 0.63 -8.34) (layer F.SilkS) (width 0.12))
(fp_line (start 1.17 25.99) (end 24.23 25.99) (layer F.Fab) (width 0.1))
(fp_line (start 24.23 25.99) (end 24.23 -6.21) (layer F.Fab) (width 0.1))
(fp_line (start 22.23 -8.21) (end 0.63 -8.21) (layer F.Fab) (width 0.1))
(fp_line (start -1.37 1) (end -1.37 19.09) (layer F.Fab) (width 0.1))
(fp_text user %R (at 11.43 10) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.62 -8.46) (end 24.48 -8.46) (layer F.CrtYd) (width 0.05))
(fp_line (start 24.48 -8.41) (end 24.48 26.24) (layer F.CrtYd) (width 0.05))
(fp_line (start 24.48 26.24) (end -1.62 26.24) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.62 26.24) (end -1.62 -8.46) (layer F.CrtYd) (width 0.05))
(fp_poly (pts (xy -2.54 -0.635) (xy -2.54 0.635) (xy -1.905 0)) (layer F.SilkS) (width 0.15))
(fp_line (start -1.35 -1.4) (end 24.25 -1.4) (layer Dwgs.User) (width 0.1))
(fp_line (start 24.25 -1.4) (end 24.25 -8.2) (layer Dwgs.User) (width 0.1))
(fp_line (start 24.25 -8.2) (end -1.35 -8.2) (layer Dwgs.User) (width 0.1))
(fp_line (start -1.35 -8.2) (end -1.35 -1.4) (layer Dwgs.User) (width 0.1))
(fp_line (start -1.35 -1.4) (end 5.45 -8.2) (layer Dwgs.User) (width 0.1))
(fp_line (start 0.65 -1.4) (end 7.45 -8.2) (layer Dwgs.User) (width 0.1))
(fp_line (start 2.65 -1.4) (end 9.45 -8.2) (layer Dwgs.User) (width 0.1))
(fp_line (start 4.65 -1.4) (end 11.45 -8.2) (layer Dwgs.User) (width 0.1))
(fp_line (start 6.65 -1.4) (end 13.45 -8.2) (layer Dwgs.User) (width 0.1))
(fp_line (start 8.65 -1.4) (end 15.45 -8.2) (layer Dwgs.User) (width 0.1))
(fp_line (start 10.65 -1.4) (end 17.45 -8.2) (layer Dwgs.User) (width 0.1))
(fp_line (start 12.65 -1.4) (end 19.45 -8.2) (layer Dwgs.User) (width 0.1))
(fp_line (start 14.65 -1.4) (end 21.45 -8.2) (layer Dwgs.User) (width 0.1))
(fp_line (start 16.65 -1.4) (end 23.45 -8.2) (layer Dwgs.User) (width 0.1))
(fp_line (start 18.65 -1.4) (end 24.25 -7) (layer Dwgs.User) (width 0.1))
(fp_line (start 20.65 -1.4) (end 24.25 -5) (layer Dwgs.User) (width 0.1))
(fp_line (start 22.65 -1.4) (end 24.25 -3) (layer Dwgs.User) (width 0.1))
(fp_line (start -1.35 -3.4) (end 3.45 -8.2) (layer Dwgs.User) (width 0.1))
(fp_line (start -1.3 -5.45) (end 1.45 -8.2) (layer Dwgs.User) (width 0.1))
(fp_line (start -1.35 -7.4) (end -0.55 -8.2) (layer Dwgs.User) (width 0.1))
(fp_line (start -1.37 19.09) (end 1.17 19.09) (layer F.Fab) (width 0.1))
(fp_line (start 1.17 19.09) (end 1.17 25.99) (layer F.Fab) (width 0.1))
(fp_line (start -1.37 -6.21) (end -1.37 -1) (layer F.Fab) (width 0.1))
(fp_line (start -1.37 1) (end -0.37 0) (layer F.Fab) (width 0.1))
(fp_line (start -0.37 0) (end -1.37 -1) (layer F.Fab) (width 0.1))
(fp_arc (start 0.63 -6.21) (end 0.63 -8.21) (angle -90) (layer F.Fab) (width 0.1))
(fp_arc (start 22.23 -6.21) (end 24.23 -6.19) (angle -90) (layer F.Fab) (width 0.1))
(fp_line (start -1.5 19.22) (end 1.04 19.22) (layer F.SilkS) (width 0.12))
(fp_line (start 1.04 19.22) (end 1.04 26.12) (layer F.SilkS) (width 0.12))
(fp_arc (start 0.63 -6.21) (end 0.63 -8.34) (angle -90) (layer F.SilkS) (width 0.12))
(fp_arc (start 22.23 -6.21) (end 24.36 -6.21) (angle -90) (layer F.SilkS) (width 0.12))
(pad 2 thru_hole oval (at 0 2.54) (size 2 1.6) (drill 1) (layers *.Cu *.Mask))
(pad 1 thru_hole rect (at 0 0) (size 2 2) (drill 1) (layers *.Cu *.Mask))
(pad 3 thru_hole oval (at 0 5.08) (size 2 1.6) (drill 1) (layers *.Cu *.Mask))
(pad 4 thru_hole oval (at 0 7.62) (size 2 1.6) (drill 1) (layers *.Cu *.Mask))
(pad 5 thru_hole oval (at 0 10.16) (size 2 1.6) (drill 1) (layers *.Cu *.Mask))
(pad 6 thru_hole oval (at 0 12.7) (size 2 1.6) (drill 1) (layers *.Cu *.Mask))
(pad 7 thru_hole oval (at 0 15.24) (size 2 1.6) (drill 1) (layers *.Cu *.Mask))
(pad 8 thru_hole oval (at 0 17.78) (size 2 1.6) (drill 1) (layers *.Cu *.Mask))
(pad 9 thru_hole oval (at 22.86 17.78) (size 2 1.6) (drill 1) (layers *.Cu *.Mask))
(pad 10 thru_hole oval (at 22.86 15.24) (size 2 1.6) (drill 1) (layers *.Cu *.Mask))
(pad 11 thru_hole oval (at 22.86 12.7) (size 2 1.6) (drill 1) (layers *.Cu *.Mask))
(pad 12 thru_hole oval (at 22.86 10.16) (size 2 1.6) (drill 1) (layers *.Cu *.Mask))
(pad 13 thru_hole oval (at 22.86 7.62) (size 2 1.6) (drill 1) (layers *.Cu *.Mask))
(pad 14 thru_hole oval (at 22.86 5.08) (size 2 1.6) (drill 1) (layers *.Cu *.Mask))
(pad 15 thru_hole oval (at 22.86 2.54) (size 2 1.6) (drill 1) (layers *.Cu *.Mask))
(pad 16 thru_hole oval (at 22.86 0) (size 2 1.6) (drill 1) (layers *.Cu *.Mask))
(model ${KISYS3DMOD}/Module.3dshapes/wemos_d1_mini_light.step
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x08_P2.54mm_Vertical.step
(offset (xyz 0 0 9.5))
(scale (xyz 1 1 1))
(rotate (xyz 0 -180 0))
)
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x08_P2.54mm_Vertical.step
(offset (xyz 22.86 0 9.5))
(scale (xyz 1 1 1))
(rotate (xyz 0 -180 0))
)
(model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_1x08_P2.54mm_Vertical.step
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
(model ${KISYS3DMOD}/Connector_PinSocket_2.54mm.3dshapes/PinSocket_1x08_P2.54mm_Vertical.step
(offset (xyz 22.86 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)

[Duckle29]

@Misca1234 I like it, I'll push that to my fork

[Misca1234]

Great, thx

[Misca1234]

Now it is just one thing left from my side, please change the .step files for the 3D model to .wrl files

You will get a bunch of new travis errors, but those will be ignored for the merge

[evanshultz]

Note the Travis errors. The footprint file above has issues with the 3D model section.

Image, which is helpful when visual changes have been made:

• The cross-hatched area isn't labelled. See http://kicad-pcb.org/libraries/klc/F4.5/.
• The description has typos.
• Is there an official drawing? The JPG linked is from a 3rd party site and doesn't include all dimensions, like corner radius.

[Duckle29]

@evanshultz I will add the text when I get home, but the rule says it may be included, not that it has to be.

As for 3D models, I'll change it to wrl if you want, but I thought it'd switch to step files with kicad 5.0?

EDIT: And I will ofc fix typos

[evanshultz]

Please do add the text. It makes it much more clear to users.

3D model references must be WRL. See http://kicad-pcb.org/libraries/klc/F9.3/. KiCad knows how to link STEP models automatically, I believe.

[Duckle29]

@evanshultz Done :)

[evanshultz]

Thanks!

There's still a typo of "column" in the description.

I can't recall ever seeing a footprint call multiple 3D models before. All your 3D models are at the default spacing and locations which definitely isn't correct. @poeschlr Can you take a look at this?

[Duckle29]

@evanshultz Fixed the spelling error. This is how the 3D looks to me:

I'm also curious to hear how to handle modules and their pin headers like this.

[evanshultz]

Still a typo. There should be a "n" at the end of "column".

Unless there is a precedent for having multiple 3D models, I think a unique, single 3D model for the entire module is best. Perhaps @poeschlr or @Shackmeister would know?

[Misca1234]

I think the multiple 3D models is ok, I found it useful when I reworked the valves.

@Duckle29
fix the typo mentioned by evan and I am happy to merge

[Misca1234]

@Duckle29
If you fix the typo and if evan is ok with multiple 3D models I think we are ready to go.

[Duckle29]

Sorry for taking my time on this. Had some exams to focus on. Turns out that was stupid, as I already had fixed this, just forgotten to push
oops

[Misca1234]

Thx

[Shackmeister]

I would generally speaking go for one single model

[herostrat]

I have a (late question) because I just noticed the name.

Why the "light" extension?
Afaik the only differences are not noticeable on the footprint but on the internal rom and ram sizes and additional mounting holes.

We should rename it without "light" imho.

See pinout the same for mini and mini light:
https://wiki.wemos.cc/products:d1:d1_mini
https://wiki.wemos.cc/products:d1:d1_mini_lite