Skip to content
This repository has been archived by the owner on Oct 2, 2020. It is now read-only.

Busses #203

Open
wants to merge 28 commits into
base: master
Choose a base branch
from
Open

Busses #203

wants to merge 28 commits into from

Conversation

DavidGriffith
Copy link

@DavidGriffith DavidGriffith commented Dec 31, 2017

Adding S100 and PC 8-bit card edge footprints and clarify the AT and PCI busses.


Thanks for creating a pull request to contribute to the KiCad libraries! To speed up integration of your PR, please check the following items:

  • Provide a URL to a datasheet for the footprint(s) you are contributing
  • An example screenshot image is very helpful
  • If there are matching symbol or 3D model PRs, provide link(s) as appropriate
  • Check the output of the Travis automated check scripts - fix any errors as required

@CLAassistant
Copy link

CLAassistant commented Dec 31, 2017

CLA assistant check
All committers have signed the CLA.

@DavidGriffith
Copy link
Author

@DavidGriffith
Copy link
Author

BUS_PC_M
bus_pc_m

@jkriege2
Copy link
Collaborator

thanks for your contribution.

Can you please give an example for a specification against which we can compare yout footprint?

Also please add a courtyrad for BUS_S100_M

@DavidGriffith
Copy link
Author

DavidGriffith commented Dec 31, 2017

What sort of specifications do you require? The PDFs I referenced contain dimensions for 8-bit ISA and S100 card edges.

@DavidGriffith
Copy link
Author

BUS_S100_M
bus_s100_m

@jkriege2
Copy link
Collaborator

uuups, sorry overread the spec PDFs ... will have a look at them ;-)

@jkriege2
Copy link
Collaborator

Hi!

generally this looks good (as fas as I saw in the specs), but I would suggest some alterations (although the other edge connectors do not follow these yet):

  • You put silkscreen, where actually the PCB edge should be cut out. Please add the PCB cuts on the layer Dwgs.User and add a commenting text on Cmts.User saying e.g. PCB edge cut next to the cut-marking. Ideally these should be on Edge.Cuts, but that is currently not possible in the editor, so we will ahve to go with Dwgs.User. Then Silkscreen should only be where there will be PCB left (most probably above the pads). Maybe you can even hint with tiny horizontal lines of 1-2mm length, where the PCB continues
  • Since this connector is not populated by any parts, you don't need the %R onf the F.Fab-layer

Best,
JAN

@poeschlr
Copy link
Collaborator

poeschlr commented Jan 1, 2018

I think the edge stuff could be directly put onto the edge cuts layer.
At least this is how it is done in for example Samtec_MECF-50-0_-L-DV_2x50_P1.27mm_Polarized_Edge.
Sadly this requires editing the footprint with a text editor.
If you do it this way make sure the end of the lines is on a quite coarse grid such that users can easily connect the rest of their edge cuts polygon to it.

If this is not how we want it to be done, then the script that generates the samtec connectors needs to be corrected and these footprints need to be re exported.

Edit: About the second reference: i would still add it because otherwise it would be missing from the documentation.

@jkriege2
Copy link
Collaborator

jkriege2 commented Jan 1, 2018

Yes, I also see the Dwgs.User as a workaround for the missing capabilities of the editor ... So if you edit the text files in a text editor that would be the ideal way, but if you work with the footprint editor, please use the Dwgs.User-layer.

Best,
JAN

@poeschlr
Copy link
Collaborator

@DavidGriffith Could you look into our suggestions?

@DavidGriffith
Copy link
Author

Here are edge cuts for the PC, AT, and S100 card edges. I also moved the courtyards to coincide with the cuts and deleted the %R references. Is this what you're looking for? If so, I'll go ahead and fix the PCI and PCIexpress footprints along the same lines.

@poeschlr
Copy link
Collaborator

poeschlr commented Feb 2, 2018

Your changes look good right now.
Could you add pin 1 markers on silk at least? (Will help users trouble shoot their board)

@DavidGriffith
Copy link
Author

I just realized that I have not yet checked to make sure the solder mask layers make sense for card edges.

@Shackmeister
Copy link
Collaborator

Hi @DavidGriffith
Soldermask settings looks pretty fine, but I have a few requests.

  • Courtyard clearance should be 0.5mm for connectors

  • shouldn't the connector's be centered around the middle instead of pin 1?

  • add a pin 1 marker on Fab layer.

  • add the same fab drawing on B.Fab

  • change the silkscreen pin 1 indicator to a small triangle or similar.

  • on the connectors with one rounded end, it would be beneficial to use custom pad shapes. (or at least make the circles same pad number)

@evanshultz
Copy link
Collaborator

Is it correct to remove the %R on the fab layer? Wouldn't it be helpful to have it on the fab layer since there are lines on that layer? If there a multiple edge connector the user wouldn't know which one is which if they're just looking at the fab layer (I realize this ref des is typically for assembly but it may be helpful so the user can see that they're stuffing parts close to J1 and not J2, for example.)

You can add the documents above to the description so we know the source for these footprint designs.

Shouldn't a 3D model be provided? Without it, the gold fingers won't show up in the 3D viewer, right?

@poeschlr
Copy link
Collaborator

The 3d model is not necessary. Footprint features are always rendered even without a model assigned.


Regarding reference i already stated above that i would like a refdes on the fab layer.

@evanshultz
Copy link
Collaborator

@poeschlr
Yep, but a commit above removed it so I wanted to surface your comment and prevent it from getting lost. :)

@Shackmeister
Copy link
Collaborator

Hi @DavidGriffith
Would it be possible for you to find some time to finish this PR? :)

@DavidGriffith
Copy link
Author

@Shackmeister, I think I applied all the requests you made except for pin-1 indicators on fab layers (how should they look?) and connectors with one rounded edge (I'm not clear on what you're asking for). I'll need to go over it all again to verify the courtyard clearances.

@DavidGriffith
Copy link
Author

Okay, that's done. How can I apply a square soldermask gap over the entirety of the gold fingers?

@evanshultz
Copy link
Collaborator

@DavidGriffith
Simply make a polygon only on the layer you want:
image

That requires two polygons, one for each layer. You could also make a single pad, only on the mask layers, and without a pin number:
image

Note that I haven't done this on these exact footprints so you should check Gerbers and make sure it's what you want, but one or both of these should work.

@DavidGriffith
Copy link
Author

Would you please explain how to get the line/polygon tool to draw a polygon? I see lots of tutorials and such discussing polygons, but nothing actually shows HOW to get that tool to draw a polygon.

@poeschlr
Copy link
Collaborator

poeschlr commented Aug 6, 2018

You need kicad 5 to manipulate polygons. If you have kicad 5 then there is a separate tool for graphical polygons. (You then have the line tool and the graphical polygon tool)

I am just not really sure what you try to achieve to be honest. A single rectangle mask only pad should already do the trick. (or two if you want the "missing pin area" covered by soldermask) If you want mask between the pins then you do not need to do anything as the mask over the pins themselfes is already removed by activating the mask layer of the pads.

@DavidGriffith
Copy link
Author

I'm trying to leave the area where the edge connector is left clear of soldermask. I don't understand what you mean by "no need to do anything" because the soldermask layer just masks off the pads (fingers) and the rest of the connector has mask applied.

@poeschlr
Copy link
Collaborator

poeschlr commented Aug 6, 2018

Read my comment again. It consists of more than one option. The no need to do anything part already mentioned that there will be soldermask left between the pads ;)

@DavidGriffith
Copy link
Author

DavidGriffith commented Aug 7, 2018

For myself and any others interested, I found a better reference for S100 card edge specs than the grainy one I referenced earlier: http://www.edac.net/dat/files/161.pdf

@evanshultz
Copy link
Collaborator

I also find it common to mask the entire edge where the fingers are, and not just between pins. This is the only way I can recall seeing it, in fact.

This library is for KiCad v5. If you're not using it, you should. You will find how to add a polygon in the Place menu, and adding a pad is nothing pad. A pad is probably easiest since it can do both sides at once.

@DavidGriffith
Copy link
Author

Ya, I was hanging on with V4 for a couple reasons. One of the bigger annoyances for me is how v5 changed the way things are toggled in the 3D view. I'm working on that right now (https://github.com/DavidGriffith/kicad-source-mirror branch "3d-viewer-mods").

For this pull, I would like for whoever might want to merge this pull request to please hold off until I declare my work complete. I'm double-checking dimensions and redoing some stuff that made sense in V4 but not anymore for V5.

The official specs at
http://www.s100computers.com/General%20Images/IEEE_696_1983.pdf clearly
states that the edge should be 6.350 inches to 6.360 inches to fit in a
slot measuring 6.375 inches.  That's easy to miss though.  According to
this data sheet (http://www.edac.net/dat/files/161.pdf) for slots
matching the spec, the slot is 6.375 inches wide and the card edge
should be 0.012 inches smaller.  EDAC makes slots of varying connector
counts matching the S100 pitch for applications other than S100.
@DavidGriffith
Copy link
Author

I think the S100 card edge is complete. I don't know if putting those strips along the bottom in F.Fab and B.Fab for beveling the card should be done in the footprint or completed board. Please comment.

@myfreescalewebpage myfreescalewebpage added Enhancement Improves existing footprint in the library Pending reviewer A pull request waiting for a reviewer labels Jan 7, 2019
@ProxyPlayerHD
Copy link

ProxyPlayerHD commented Jul 9, 2020

I'm sorry but has this ever been added to the program? I'm not 100% sure how it works.

I can find both the 8 and 16 bit ISA connector symbols but neither have a footprint (though the 16 bit one has a footprint "BUS_AT" but it's not assigned by default.)

EDIT: Nvm i just made my own version but cutting off excess pins from the 16 bit one. still a shame the 8 bit one is not standard in KiCad.

Sign up for free to subscribe to this conversation on GitHub. Already have an account? Sign in.
Labels
Enhancement Improves existing footprint in the library Pending reviewer A pull request waiting for a reviewer
Projects
None yet
Development

Successfully merging this pull request may close these issues.

8 participants