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1. VLSI-Task1 VLSI-Task1 Public

   VLSI Internship Task 1 - Basic Logic Gates and Half Adder Implementation using CircuitVerse.

2. VLSI-Task2 VLSI-Task2 Public

   VLSI Internship Task 2 - Verilog HDL Implementation and Simulation of Logic Gates, Half Adder, and Full Adder using EDA Playground

3. EPBL_Internship EPBL_Internship Public

   Design and FPGA implementation of a starvation-free adaptive priority traffic controller using Verilog HDL.

   Verilog