context example

Author: Kazhuu

language-features/context/test.vhd

@@ -1,4 +1,7 @@
+-- Make library visible to design.
 library test_lib;
+-- Apply test_lib context to this design. This will include context includes
+-- visible to this design. No need to write or import ieee stuff.
 context test_lib.lib_context;
 
 
@@ -8,11 +11,20 @@ end entity;
 
 architecture tb of test is
 
-    signal test : std_logic := '1';
+    -- std_logic type available because of the context.
+    signal a, b, s : std_logic := '0';
+    signal d : std_logic;
     signal end_simulation : boolean := true;
 
 begin
-    -- TODO: Write rest of this here.
+
+    -- Mux component available because of the context.
+    mux1 : entity mux port map(a, b, s, d);
+
+    end_simulation <= false after 1 ps;
+    assert end_simulation
+    report "simulation ended"
+    severity failure;
 
 end architecture;
 

language-features/context/test_lib/lib_context.vhd

@@ -1,5 +1,11 @@
+-- Declare context which can be used in some other design with context
+-- keyword. This is like an entry point to this library.
+-- Using context make inlcuding multiple libraries less tedious and
+-- easier. This context is compiled to test_lib library.
 context lib_context is
     library ieee;
     use ieee.std_logic_1164.all;
+    -- Notice no library statement needed, because this file is compiled
+    -- to the test_lib library.
     use test_lib.all;
 end context;

language-features/context/test_lib/mux.vhd

@@ -2,6 +2,7 @@ library ieee;
 use ieee.std_logic_1164.all;
 
 
+-- Compiled to test_lib library.
 entity mux is
     port (
         a, b, s : in std_logic;