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context keyword
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language-features/context/test.vhd

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library test_lib;
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context test_lib.lib_context;
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entity test is
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end entity;
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architecture tb of test is
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signal test : std_logic := '1';
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signal end_simulation : boolean := true;
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begin
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-- TODO: Write rest of this here.
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end architecture;
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context lib_context is
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library ieee;
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use ieee.std_logic_1164.all;
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use test_lib.all;
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end context;
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library ieee;
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use ieee.std_logic_1164.all;
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entity mux is
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port (
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a, b, s : in std_logic;
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d : out std_logic
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);
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end entity;
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architecture rtl of mux is
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begin
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d <= b when s = '1' else a;
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end architecture;

language-features/context/vimhdl.prj

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builder = msim
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target_dir = .build
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vhdl test_lib test_lib/mux.vhd -2008
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vhdl test_lib test_lib/lib_context.vhd -2008
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vhdl work test.vhd -2008

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