wait until

Author: Kazhuu

README.md

@@ -32,3 +32,4 @@ Testbench will run, print results and then stop automatically.
 * Different wait statements with process.
 * Example components?
 * Three main different ways to implement state machines.
+* Use VUnit to implement basic testing examples.

language-features/context/test_lib/lib_context.vhd

@@ -1,6 +1,6 @@
 -- Declare context which can be used in some other design with context
 -- keyword. This is like an entry point to this library.
--- Using context make inlcuding multiple libraries less tedious and
+-- Using context make including multiple libraries less tedious and
 -- easier. This context is compiled to test_lib library.
 context lib_context is
     library ieee;

language-features/wait-statements/vimhdl.prj

@@ -0,0 +1,4 @@
+builder = msim
+target_dir = .build
+
+vhdl work wait-until.vhd -2002

language-features/wait-statements/wait-until.vhd

@@ -0,0 +1,44 @@
+-- Wait until statement can be used in processes to suspend its execution until
+-- given expressions becomes true.
+
+-- This example code will print following messages:
+-- Note: before wait until
+-- Note: after wait until
+-- Note: before wait until
+-- Failure: simulation ended
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity wait_until is
+end entity;
+
+
+architecture tb of wait_until is
+
+    signal test : boolean := false;
+    signal end_simulation : boolean := true;
+
+begin
+
+    test <= true after 1 ps;
+
+    -- Process will execute until wait statement and suspends until test signal
+    -- changes to true. After that execution continues until wait statements is
+    -- executed again. This causes process to be suspended again until event
+    -- happens on the test signal. This is the reason also why first message is
+    -- printed twice.
+    main : process
+    begin
+        report "before wait until";
+        wait until test;
+        report "after wait until";
+    end process;
+
+    end_simulation <= false after 2 ps;
+    assert end_simulation
+    report "simulation ended"
+    severity failure;
+
+end architecture;

run.py

@@ -2,5 +2,5 @@
 
 vu = VUnit.from_argv()
 lib = vu.add_library('lib')
-lib.add_source_files("components/arithmetic/array-multiplier/*.vhd")
+lib.add_source_files("components-and-cores/arithmetic/array-multiplier/*.vhd")
 vu.main()