drm/radeon: fix typo in finding PLL params

Otherwise the limit is raised to high. Signed-off-by: Christian König <christian.koenig@amd.com> Tested-by: Ken Moffat <zarniwhoop@ntlworld.com>
Katya-Incorporated · May 20, 2014 · 74ad54f · 74ad54f
1 parent 4955bb0
commit 74ad54f
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
@@ -999,7 +999,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
 
 	/* avoid high jitter with small fractional dividers */
 	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
-		fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60);
+		fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
 		if (fb_div < fb_div_min) {
 			unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
 			fb_div *= tmp;