Having trouble with Cosimulation

[ttaehyung]

Hello!
Currently I'm working on the very first project, FIR11 project.
I've done with c simulation and synthesis successfully.
However, cosimulation always fails with error code COSIM [212-4].
Should I set something else to run cosimulation?
Following is the full error and warning message when I run cosimulation on Vitis HLS:

ERROR: [COSIM 212-4] *** C/RTL co-simulation finished: FAIL *** FIR1:solution1 Jul 30, 2021, 3:33:33 AM
WARNING: [Simtcl 6-197] One or more HDL objects could not be logged because of object type or size limitations. To see details
please rerun the command with -verbose (-v).

set designtopgroup [add_wave_group "Design Top Signals"]

set coutputgroup [add_wave_group "C Outputs" -into $designtopgroup]

set return_group [add_wave_group return(wire) -into $coutputgroup]

add_wave /apatb_fir_top/AESL_inst_fir/y_ap_vld -into $return_group -color #ffff00 -radix hex

add_wave /apatb_fir_top/AESL_inst_fir/y -into $return_group -radix hex

set cinputgroup [add_wave_group "C Inputs" -into $designtopgroup]

set return_group [add_wave_group return(wire) -into $cinputgroup]

add_wave /apatb_fir_top/AESL_inst_fir/x -into $return_group -radix hex

set blocksiggroup [add_wave_group "Block-level IO Handshake" -into $designtopgroup]

add_wave /apatb_fir_top/AESL_inst_fir/ap_start -into $blocksiggroup

add_wave /apatb_fir_top/AESL_inst_fir/ap_done -into $blocksiggroup

add_wave /apatb_fir_top/AESL_inst_fir/ap_idle -into $blocksiggroup

add_wave /apatb_fir_top/AESL_inst_fir/ap_ready -into $blocksiggroup

set resetgroup [add_wave_group "Reset" -into $designtopgroup]

add_wave /apatb_fir_top/AESL_inst_fir/ap_rst -into $resetgroup

set clockgroup [add_wave_group "Clock" -into $designtopgroup]

add_wave /apatb_fir_top/AESL_inst_fir/ap_clk -into $clockgroup

set testbenchgroup [add_wave_group "Test Bench Signals"]

set tbinternalsiggroup [add_wave_group "Internal Signals" -into $testbenchgroup]

set tb_simstatus_group [add_wave_group "Simulation Status" -into $tbinternalsiggroup]

set tb_portdepth_group [add_wave_group "Port Depth" -into $tbinternalsiggroup]

add_wave /apatb_fir_top/AUTOTB_TRANSACTION_NUM -into $tb_simstatus_group -radix hex

add_wave /apatb_fir_top/ready_cnt -into $tb_simstatus_group -radix hex

add_wave /apatb_fir_top/done_cnt -into $tb_simstatus_group -radix hex

add_wave /apatb_fir_top/LENGTH_y -into $tb_portdepth_group -radix hex

add_wave /apatb_fir_top/LENGTH_x -into $tb_portdepth_group -radix hex

set tbcoutputgroup [add_wave_group "C Outputs" -into $testbenchgroup]

set tb_return_group [add_wave_group return(wire) -into $tbcoutputgroup]

add_wave /apatb_fir_top/y_ap_vld -into $tb_return_group -color #ffff00 -radix hex

add_wave /apatb_fir_top/y -into $tb_return_group -radix hex

set tbcinputgroup [add_wave_group "C Inputs" -into $testbenchgroup]

set tb_return_group [add_wave_group return(wire) -into $tbcinputgroup]

add_wave /apatb_fir_top/x -into $tb_return_group -radix hex

save_wave_config fir.wcfg

run all

////////////////////////////////////////////////////////////////////////////////////
// Inter-Transaction Progress: Completed Transaction / Total Transaction
// Intra-Transaction Progress: Measured Latency / Latency Estimation * 100%
//
// RTL Simulation : "Inter-Transaction Progress" ["Intra-Transaction Progress"] @ "Simulation Time"
////////////////////////////////////////////////////////////////////////////////////
// RTL Simulation : 0 / 600 [0.00%] @ "110000"
// RTL Simulation : 1 / 600 [100.00%] @ "174000"
// RTL Simulation : 2 / 600 [100.00%] @ "238000"

......
// RTL Simulation : 600 / 600 [100.00%] @ "38510000"
////////////////////////////////////////////////////////////////////////////////////
$finish called at time : 38534 ns : File "/home/centos/src/project_data/aws-fpga/Vitis/intern/FIR1/solution1/sim/verilog/fir.autotb.v"
Line 279

quit FIR1:solution1 Jul 30, 2021, 3:14:52 AM

WARNING: [HLS 200-626] This design is unable to schedule all read ports in the first II cycle. The RTL testbench may treat
the design as non-pipelined FIR1:solution1 Jul 30, 2021, 3:14:26 AM