Pinned Loading

1. VSD_RISC-V_SoC_Tapeout_Program VSD_RISC-V_SoC_Tapeout_Program Public

   Hands-on SoC design journey from RTL to GDSII using open-source EDA. Part of the VSD RISC-V Reference SoC Tapeout Program, covering RTL sim, synthesis, GLS, STA, floorplan, placement, routing, and …

   Verilog

2. RTL2GDS RTL2GDS Public

   This project focuses on the design, verification, and physical implementation (RTL to GDSII) of full adder circuits using two architectural approaches: flat and hierarchical design methodologies. T…

3. OpenROAD-for-Low-cost-ASIC-design-and-Rapid-Innovation OpenROAD-for-Low-cost-ASIC-design-and-Rapid-Innovation Public

   This workshop was organised by IIT Guwahati collabarted with MeitY, NINE Labs, Electronics India.

   Verilog 3

4. Physical-Design Physical-Design Public

5. Design-and-Analysis-of-a-CMOS-Inverter-Using-the-Sky130PDK Design-and-Analysis-of-a-CMOS-Inverter-Using-the-Sky130PDK Public

   3

6. Signing-off-Timing-Analysis Signing-off-Timing-Analysis Public