jitlayers: Enable FastISel on AArch64 at -O0/-O1 #60338
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FastISel was disabled on AArch64 in 2015 (PR JuliaLang#13393) to fix issue JuliaLang#13321, but that issue was specifically about 32-bit ARM (ARMv7) segfaults during bootstrap. The AArch64 exclusion was added conservatively alongside the ARM fix. AArch64 FastISel has been actively maintained upstream with recent bug fixes: - llvm/llvm-project#75993 (Jan 2024) - llvm/llvm-project#133987 (May 2025) This enables faster instruction selection for JIT compilation on AArch64 at lower optimization levels, reducing compilation latency.
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Both this and #60339 are green. That PR is the more correct choice today, if I understand correctly. |
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I disabled it because we've seen several miscompiles on it. |
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Ok. As you mention over in #60339 lets try that out. |
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FastISel was disabled on AArch64 in #13393 to fix issue #13321, but that issue was specifically about 32-bit ARM (ARMv7) segfaults during bootstrap. AFAICT the AArch64 exclusion was added conservatively alongside the ARM fix.
AArch64 FastISel has been actively maintained upstream with recent bug fixes:
This enables faster instruction selection for JIT compilation on AArch64 at lower optimization levels, reducing compilation latency.
Co-authored-by: Claude