Interactive Memory Game (FPGA Implementation)

Project Overview

This project implements a digital memory game that tests whether a subject can correctly enter a predefined sequence of button presses (ABAABBABABA). If successful, the system simulates a reward using a green LED; if incorrect, it simulates a penalty with a red LED and resets. The design began as a finite state machine and was later fully implemented in Verilog, then deployed on the Nexys A7-100T FPGA.

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Verilog HDL Implementation

The core logic of the game was written in Verilog. The implementation includes modular design, clock division, and full testbench verification.

📁 Modules Overview

• jkFlipFlop
  A basic JK flip-flop module, triggered on the clock's rising edge.

• InputFlipFlop
  A sequential logic unit using four JK flip-flops to track button sequences (X1 and X2) and represent system state.

• OutputFlipFlop
  Generates output indicators (Z1 to Z12) based on the internal state. These outputs control the progress, shock, and reward LEDs.

• TopModule
  Integrates the input and output modules and connects to external I/O.

• ClockDivider
  Divides the system clock to a slower frequency for human-observable LED changes.

🧪 Testbench (tb_MemoryGame.v)

The testbench simulates the complete button sequence under different conditions and verifies all expected LED outputs. It also tests invalid inputs (e.g., simultaneous button presses) to confirm error handling.

🖼️ Simulation Output

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FPGA Deployment (Nexys A7-100T)

The Verilog design was synthesized and deployed on a Digilent Nexys A7-100T FPGA board using Xilinx Vivado.

⚙️ Hardware Setup Steps

1. Constraints File (.xdc)
   Created to map Verilog I/Os (X1, X2, Z1-Z12) to the Nexys A7’s physical pins.

2. Synthesis and Implementation
   Verilog files imported to Vivado → synthesized → implemented with successful timing and resource mapping.

3. Bitstream Generation and Upload
   Generated .bit file was uploaded via USB to configure the FPGA.

4. Physical Testing
   Button presses were simulated via switches or external input, and LED behavior was verified for all sequences.

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🎥 Demo Videos

🔧 Hardware Demo on Nexys A7-100T:

Demo.mov

🧪 Simulation in Logisim:

StateMachine.mp4

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🧠 Click to view the original FSM design process

Original FSM Design

Description

Originally, this project was a conceptual state machine design, developed using standard digital logic techniques before moving to HDL implementation.

Circuit Behavior Summary

1. System starts in idle state until a button is pressed.
2. Correct button → progress LED (yellow) lights up.
3. Incorrect button or simultaneous press → shock (red LED), reset.
4. Successful sequence → reward (green LED), reset.

📊 State Diagram

🧮 State Table and Excitation Table

📐 Equations and Schematic

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🔚 Conclusion

This project demonstrated the full lifecycle of a digital system—from concept and theoretical design to Verilog implementation, simulation, and FPGA deployment. Building and testing this memory game provided hands-on experience in modular HDL design, timing control, testbench development, and hardware interfacing.

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