Fix #1310: LDRSW (literal)

JonathanSalwan · Mar 11, 2024 · 924bcbb · 924bcbb
1 parent 06610ca
commit 924bcbb
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Showing 3 changed files with 19 additions and 1 deletion.
diff --git a/.build_number b/.build_number
@@ -1 +1 @@
-1590
+1591
diff --git a/src/libtriton/arch/arm/aarch64/aarch64Semantics.cpp b/src/libtriton/arch/arm/aarch64/aarch64Semantics.cpp
@@ -3385,6 +3385,11 @@ namespace triton {
           triton::arch::OperandWrapper& dst = inst.operands[0];
           triton::arch::OperandWrapper& src = inst.operands[1];
 
+          /* LDRSW (literal) */
+          if (inst.operands.size() == 2 && src.getType() == triton::arch::OP_IMM) {
+            src = triton::arch::MemoryAccess(src.getConstImmediate().getValue(), dst.getSize());
+          }
+
           /* Create symbolic operands */
           auto op = this->symbolicEngine->getOperandAst(inst, src);
 

diff --git a/src/testers/unittests/test_github_issues.py b/src/testers/unittests/test_github_issues.py
@@ -648,6 +648,19 @@ def test_2(self):
         x0 = self.ctx.getConcreteRegisterValue(self.ctx.registers.x0)
         self.assertEqual(x0, 0x55667788)
 
+class TestIssue1310(unittest.TestCase):
+    """Testing #1310."""
+
+    def setUp(self):
+        self.ctx = TritonContext(ARCH.AARCH64)
+        self.ctx.setConcreteMemoryAreaValue(0x400000+0x30, b'\x72\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00')
+
+    def test_1(self):
+        inst = Instruction(0x400000, b'\x91\x01\x00\x98') # ldrsw x17, #0x30
+        self.ctx.processing(inst)
+        x17 = self.ctx.getConcreteRegisterValue(self.ctx.registers.x17)
+        self.assertEqual(x17, 0x72)
+
 
 # FIXME: Uncomment this one when we will move to Capstone 5 as min version
 #class TestIssue1195(unittest.TestCase):