SNES CPU

CPU

The CPU of the Super Nintendo is the microprocessor Ricoh 5A22, based on the 16-bit 65C816 microprocessor.

65C816 microprocessor

The 65C816 is a little endian microprocessor, meaning the least significant byte is at the lowest address.

e.g. $56 ($ means hexadecimal), represented in binary as 0101 0110 will be stored as 0110 0101 in memory.

Native and Emulation modes

The 65C816 features two modes of operation:

• Native mode
  • 256 opcodes for 92 instructions with 24 addressing modes.
  • 16-bit arithmetic.
• Emulation mode (acts like the 6502 NES CPU)
  • 212 opcodes and 69 instructions with 16 addressing modes.
  • 8-bit arithmetic.

Most of the opcodes are shared between the two modes, the difference being on how many bytes they operate. In emulation mode, the remaining opcodes are noop.

Upon booting, the CPU is set in emulation mode, thus acting like a 6502.

Registers

• P - Status (8-bit).
• A - Accumulator (8-bit / 16-bit).
• X - Index X (8-bit / 16-bit).
• Y - Index Y (8-bit / 16-bit).
• SP - Stack Pointer (8-bit).
• DP - Direct Page (16-bit).
• PC - Program Counter (16-bit).
• PB - Program Bank (8-bit).
• E - Emulation (8-bit).

Status register

The status register holds precious information about the execution of instructions, the flags are listed in the respective order:

• C - Carry.
• Z - Zero.
• I - IRQ Disable.
• D - Decimal.
• X - Index size.
• M - Accumulator size.
• V - Overflow.
• N - Negative.

Upon booting, the status register is set to #00101100 (Flags set to $1: IRQ Disable, Index size and Accumulator size).

Accumulator register

The accumulator register is used for math operations, it can either hold an operand or an arithmetic result.

CLC ; Clears the carry bit, most arithmetic operations are altered by the carry bit.
ADC #20 ; Adds $20 to the accumulator.

• Emulation mode
  • The accumulator is a 8-bit register and is often referred as Accumulator A.
• Native mode
  • The accumulator size can either be 8-bit or 16-bit depending on the Status Register Flag M:
    • If Flag M is set, it is an 8-bit register (cf Emulation mode).
    • If Flag M is clear, it is a 16-bit register "packed" into two bytes: A (8 lowest bits) and B (8 highest bits) and is often referred as Accumulator C.

Upon booting, the accumulator register is set to $0 (and is 8-bit wide as the CPU starts in emulation mode).

Index X register

Generally used in indexed X addressing modes, where the index is added to the effective address

• Emulation mode
• The index is a 8-bit register
• Native mode
• The index is a 16-bit register (switching from emulation mode to native mode set the 8 high order bits to zero).

Upon booting, the index X register is set to $0

Index Y register

Same usage as Index X for indexed Y addressing modes

Upon booting, the index Y register is set to $0

Stack Pointer register

Upon booting, the stack pointer register is set to $100

Direct Page register

Alias: DP register, D register

Upon booting, the direct page register is set to $0

Program Counter register

Program Bank register

Alias: PB register, K register

Upon booting, the program bank register is set to $0

Emulation register

The emulation register is an hidden bit in the CPU, it tells whether the CPU is in native or emulation mode.

One can only alter the emulation register with the XCE (eXchange Carry and Emulation bits) instruction that changes the native/emulation mode of the CPU.

SEC ; Sets the carry bit.
XCE ; Enables emulation mode.

---

CLC; Clears the carry bit.
XCE ; Enables native mode.