Skip to content
View JessePS120's full-sized avatar

Organizations

@UA-BattChallenge

Block or report JessePS120

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. NUCLEO-Cache-Simulator NUCLEO-Cache-Simulator Public

    Configurable CPU cache simulator on an STM32L476RG Nucleo, using UART and DMA to stream address traces and report tag/index/offset decoding and hit rates.

    C 1

  2. PagingSimulator PagingSimulator Public

    Virtual memory paging simulator in C: logical-to-physical address translation with a FIFO TLB, demand paging from a backing store, and LRU frame replacement.

    C 1

  3. UDSCANTool UDSCANTool Public

    UDS (ISO 14229-1) diagnostic tester over ISO-TP (ISO 15765-2) and CAN 2.0B, built on an STM32G474 Nucleo. Requirements-driven with a traceability matrix.

    C 2

  4. VHDL-FSM VHDL-FSM Public

    Structural and behavioral VHDL digital design in Quartus: a from-scratch serial adder with gate-level propagation delays, a 74LS194A-style bidirectional shift register, and Moore FSMs implemented b…

    VHDL 1