develop

README.md

@@ -332,10 +332,6 @@ Where the testbench structure is,
 
     _A synchronous lifo using dual-port synchronous RAM._
 
-  * [lifo_asynchronous](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/memory/lifo_asynchronous)
-
-    _An asynchronous lifo using dual-port asynchronous RAM._
-
 * REGISTERS
 
   * [jeff_74x377](https://github.com/JeffDeCola/my-verilog-examples/tree/master/sequential-logic/registers/jeff_74x377)

basic-code/sequential-logic/d_flip_flop_pos_edge_sync_en/README.md

@@ -133,7 +133,6 @@ The output of the test,
 ```text
 TEST START --------------------------------
 
-
                  | TIME(ns) | EN | D |  Q  |
                  ---------------------------
    1        INIT |       15 | 1  | 0 |  0  |

basic-code/sequential-logic/d_flip_flop_pos_edge_sync_en/d_flip_flop_pos_edge_sync_en_tb.v

@@ -58,7 +58,6 @@ module D_FLIP_FLOP_POS_EDGE_SYNC_EN_TB ();
         $display();
         $display("TEST START --------------------------------");
         $display();
-        $display("                               ");
         $display("                 | TIME(ns) | EN | D |  Q  |");
         $display("                 ---------------------------");
         // $monitor("%4d  %10s | %8d | %d  | %1d |  %1d  |", VECTORCOUNT, COMMENT, $time, EN, D, Q_beh);

basic-code/sequential-logic/jk_flip_flop_pos_edge_sync_clear/README.md

@@ -149,7 +149,6 @@ The output of the test,
 ```text
 TEST START --------------------------------
 
-
                  | TIME(ns) | CLRBAR | J | K |  Q  |
                  -----------------------------------
    1        INIT |       22 |   1    | 0 | 0 |  x  |

basic-code/sequential-logic/jk_flip_flop_pos_edge_sync_clear/jk_flip_flop_pos_edge_sync_clear_tb.v

@@ -58,7 +58,6 @@ module JK_FLIP_FLOP_POS_EDGE_SYNC_CLEAR_TB ();
         $display();
         $display("TEST START --------------------------------");
         $display();
-        $display("                                      ");
         $display("                 | TIME(ns) | CLRBAR | J | K |  Q  |");
         $display("                 -----------------------------------");
         // $monitor("%4d  %10s | %8d |   %1d    | %1d | %1d |  %1d  |", VECTORCOUNT, COMMENT, $time, CLRBAR, J, K, Q_beh);

sequential-logic/memory/dual_port_ram_asynchronous/README.md

@@ -67,7 +67,7 @@ behavioral model,
         if (we_A) begin
             mem[addr_A] <= data_in_A;
             data_out_A <= data_in_A;
-        // READ    
+        // READ
         end else begin
             data_out_A <= mem[addr_A];
         end

sequential-logic/memory/dual_port_ram_asynchronous/dual_port_ram_asynchronous.v

@@ -29,7 +29,7 @@ module dual_port_ram_asynchronous_behavioral(
         if (we_A) begin
             mem[addr_A] <= data_in_A;
             data_out_A <= data_in_A;
-        // READ    
+        // READ
         end else begin
             data_out_A <= mem[addr_A];
         end

sequential-logic/memory/dual_port_ram_synchronous/README.md

@@ -65,7 +65,7 @@ behavioral model,
         if (we_A) begin
             mem[addr_A] <= data_in_A;
             data_out_A <= data_in_A;
-        // READ    
+        // READ
         end else begin
             data_out_A <= mem[addr_A];
         end

sequential-logic/memory/lifo_synchronous/README.md

@@ -116,7 +116,7 @@ would take up more real estate than it's worth.
         if (rst) begin
             wrt_ptr <= 4'b0000;
             rd_ptr <= 4'b0000;
-        // BOTTOM - PUSH    
+        // BOTTOM - PUSH
         end else if ((wrt_ptr == 4'b0000) & (w_next)) begin
             wrt_ptr <= wrt_ptr + 1;
         // BOTTOM - POP
@@ -126,7 +126,7 @@ would take up more real estate than it's worth.
         end else if (w_next) begin
             wrt_ptr <= wrt_ptr + 1;
             rd_ptr <= rd_ptr + 1;
-        // POP    
+        // POP
         end else if (r_next) begin
             wrt_ptr <= wrt_ptr - 1;
             rd_ptr <= rd_ptr - 1;

sequential-logic/memory/lifo_synchronous/source/stack_ptr_control.v

@@ -14,7 +14,7 @@ module stack_ptr_control (
         if (rst) begin
             wrt_ptr <= 4'b0000;
             rd_ptr <= 4'b0000;
-        // BOTTOM - PUSH    
+        // BOTTOM - PUSH
         end else if ((wrt_ptr == 4'b0000) & (w_next)) begin
             wrt_ptr <= wrt_ptr + 1;
         // BOTTOM - POP
@@ -24,7 +24,7 @@ module stack_ptr_control (
         end else if (w_next) begin
             wrt_ptr <= wrt_ptr + 1;
             rd_ptr <= rd_ptr + 1;
-        // POP    
+        // POP
         end else if (r_next) begin
             wrt_ptr <= wrt_ptr - 1;
             rd_ptr <= rd_ptr - 1;

sequential-logic/memory/single_port_ram_synchronous/README.md

@@ -63,7 +63,7 @@ behavioral model,
         if (we) begin
             mem[addr] <= data_in;
             data_out <= data_in;
-        // READ    
+        // READ
         end else begin
             data_out <= mem[addr];
         end

sequential-logic/memory/single_port_ram_synchronous/single_port_ram_synchronous.v

@@ -21,7 +21,7 @@ module single_port_ram_synchronous_behavioral(
         if (we) begin
             mem[addr] <= data_in;
             data_out <= data_in;
-        // READ    
+        // READ
         end else begin
             data_out <= mem[addr];
         end