Verilog code for fast binary multipliers, using Vedic mathematics.
These codes were developed using Intel Quartus Prime Lite 18.1, and ModelSim Altera, implemented in the MAX10 10M50DAF484C7G FPGA.
Any questions feel free to send an email to d2022004055@unifei.edu.br
References: J. G. M. Oliveira, R. L. Moreno, O. de Oliveira Dutra and T. C. Pimenta, "Implementation of a reconfigurable neural network in FPGA," 2017 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS), Cozumel, Mexico, 2017, pp. 41-44, doi: 10.1109/ICCDCS.2017.7959699.