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fix: several bugs #80

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Merged
rewired-gh merged 1 commit into from
May 27, 2023
Merged

fix: several bugs #80

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43 changes: 25 additions & 18 deletions src/src/memory/UncachedAgent.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -52,28 +52,32 @@ class UncachedAgent extends Module {
io.accessPort.res.isFailed := DontCare // Successful
io.accessPort.res.read.data := DontCare

switch(stateReg) {
is(State.ready) {
io.accessPort.req.isReady := true.B
when(io.accessPort.req.client.isValid) {
when(axiMaster.io.readyOut) {
// Send new request
newReq := true.B
def handleRequest() = {
io.accessPort.req.isReady := true.B
when(io.accessPort.req.client.isValid) {
when(axiMaster.io.readyOut) {
// Send new request
newReq := true.B

// Next state: Wait for response
stateReg := State.waitRes
}.otherwise {
// Persist the request
lastReg.addr := io.accessPort.req.client.addr
lastReg.data := io.accessPort.req.client.write.data
lastReg.rw := io.accessPort.req.client.rw
lastReg.mask := io.accessPort.req.client.mask
// Next state: Wait for response
stateReg := State.waitRes
}.otherwise {
// Persist the request
lastReg.addr := io.accessPort.req.client.addr
lastReg.data := io.accessPort.req.client.write.data
lastReg.rw := io.accessPort.req.client.rw
lastReg.mask := io.accessPort.req.client.mask

// Next state: Wait for AXI master ready
stateReg := State.waitReady
}
// Next state: Wait for AXI master ready
stateReg := State.waitReady
}
}
}

switch(stateReg) {
is(State.ready) {
handleRequest()
}
is(State.waitReady) {
when(axiMaster.io.readyOut) {
// Send the persisted request
Expand All @@ -96,6 +100,9 @@ class UncachedAgent extends Module {

// Next state: Ready for new request
stateReg := State.ready

// Also now it is equivilent to ready state
handleRequest()
}
}
}
Expand Down
71 changes: 45 additions & 26 deletions src/src/pipeline/execution/ExeStage.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -131,39 +131,54 @@ class ExeStage extends Module {

// ALU output

// write-back information fallback
gprWriteReg.en := false.B
gprWriteReg.addr := zeroWord
gprWriteReg.data := zeroWord
when(isBlocking) {
io.instInfoPassThroughPort.out := InstInfoNdPort.default
}

val gprWriteWire = WireDefault(RfWriteNdPort.default)
val memRequestWire = WireDefault(MemRequestNdPort.default)

when(!isBlocking) {
switch(stateReg) {
is(State.blocking) {
io.gprWritePort := gprWriteWire
io.memAccessPort := memRequestWire
}
is(State.nonBlocking) {
gprWriteReg := gprWriteWire
memRequestReg := memRequestWire
}
}
}

// write-back information selection
when(!isBlocking) {
gprWriteReg.en := selectedExeInst.gprWritePort.en
gprWriteReg.addr := selectedExeInst.gprWritePort.addr
gprWriteWire.en := selectedExeInst.gprWritePort.en
gprWriteWire.addr := selectedExeInst.gprWritePort.addr

switch(selectedExeInst.exeSel) {
is(Sel.logic) {
io.freePorts.en := gprWriteReg.en
gprWriteReg.data := alu.io.result.logic
io.freePorts.en := gprWriteWire.en
gprWriteWire.data := alu.io.result.logic
}
is(Sel.shift) {
io.freePorts.en := gprWriteReg.en
gprWriteReg.data := alu.io.result.shift
io.freePorts.en := gprWriteWire.en
gprWriteWire.data := alu.io.result.shift
}
is(Sel.arithmetic) {
io.freePorts.en := gprWriteReg.en
gprWriteReg.data := alu.io.result.arithmetic
io.freePorts.en := gprWriteWire.en
gprWriteWire.data := alu.io.result.arithmetic
}
is(Sel.jumpBranch) {
io.freePorts.en := gprWriteReg.en
gprWriteReg.data := selectedPc + 4.U
io.freePorts.en := gprWriteWire.en
gprWriteWire.data := selectedPc + 4.U
}
}

switch(selectedExeInst.exeOp) {
is(ExeInst.Op.csrrd) {
io.freePorts.en := gprWriteReg.en
gprWriteReg.data := selectedExeInst.csrData
io.freePorts.en := gprWriteWire.en
gprWriteWire.data := selectedExeInst.csrData
}
}
}
Expand All @@ -185,16 +200,16 @@ class ExeStage extends Module {
instInfoReg.exceptionRecords(Csr.ExceptionIndex.ale) := isAle

when(!isBlocking) {
memRequestReg.isValid := (memReadEn || memWriteEn) && !isAle
memRequestReg.addr := Cat(loadStoreAddr(wordLength - 1, 2), 0.U(2.W))
memRequestReg.write.data := selectedExeInst.rightOperand
memRequestReg.read.isUnsigned := memLoadUnsigned
memRequestReg.rw := Mux(memWriteEn, ReadWriteSel.write, ReadWriteSel.read)
memRequestWire.isValid := (memReadEn || memWriteEn) && !isAle
memRequestWire.addr := Cat(loadStoreAddr(wordLength - 1, 2), 0.U(2.W))
memRequestWire.write.data := selectedExeInst.rightOperand
memRequestWire.read.isUnsigned := memLoadUnsigned
memRequestWire.rw := Mux(memWriteEn, ReadWriteSel.write, ReadWriteSel.read)
// mask
val maskEncode = loadStoreAddr(1, 0)
switch(selectedExeInst.exeOp) {
is(ExeInst.Op.ld_b, ExeInst.Op.ld_bu, ExeInst.Op.st_b) {
memRequestReg.mask := Mux(
memRequestWire.mask := Mux(
maskEncode(1),
Mux(maskEncode(0), "b1000".U, "b0100".U),
Mux(maskEncode(0), "b0010".U, "b0001".U)
Expand All @@ -204,11 +219,11 @@ class ExeStage extends Module {
when(maskEncode(0)) {
isAle := true.B // 未对齐
}
memRequestReg.mask := Mux(maskEncode(1), "b1100".U, "b0011".U)
memRequestWire.mask := Mux(maskEncode(1), "b1100".U, "b0011".U)
}
is(ExeInst.Op.ld_w, ExeInst.Op.ll, ExeInst.Op.st_w, ExeInst.Op.sc) {
isAle := maskEncode.orR
memRequestReg.mask := "b1111".U
isAle := maskEncode.orR
memRequestWire.mask := "b1111".U
}
}
}
Expand Down Expand Up @@ -247,14 +262,18 @@ class ExeStage extends Module {
when(io.pipelineControlPort.clear) {
gprWriteReg := RfWriteNdPort.default
InstInfoNdPort.invalidate(instInfoReg)
memRequestReg := MemRequestNdPort.default
memRequestReg := MemRequestNdPort.default
io.gprWritePort := RfWriteNdPort.default
io.memAccessPort := MemRequestNdPort.default
}

// Flush
when(io.pipelineControlPort.flush) {
gprWriteReg.en := false.B
InstInfoNdPort.invalidate(instInfoReg)
memRequestReg.isValid := false.B
io.gprWritePort := RfWriteNdPort.default
io.memAccessPort := MemRequestNdPort.default

stateReg := State.nonBlocking
exeInstStoreReg := ExeInstNdPort.default
Expand Down
2 changes: 2 additions & 0 deletions src/src/pipeline/mem/MemReqStage.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,8 @@ class MemReqStage extends Module {
val dataMask = Output(UInt((Width.Mem._data / byteLength).W))
})

// TODO: Persist input for stalling and use the persisted one as output

// Persist for stalling
val isLastStall = RegNext(io.pipelineControlPort.stall, false.B)
val translatedMemRequestReg =
Expand Down