fix: fix bug in Cu #57
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…ou CANNOT and SHOULDN't fetch and store the next bad-ass instruction to the god-damned temporary instruction storing thingy, as well as a previous stall is not meant to be waiting for issue
fix: Bad syntax and typo
…id-cpu into bug-flush
…cpu into bug-flush
rewired-gh
approved these changes
May 22, 2023
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If it is a bug in Chisel or CIRCT, please report it through opening a new issue in their repositories. |
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原来的写法生成verilog的时候生成了高阻态，不知道为什么，只能换成一种蠢写法