refactor: refactor some bundle port with parameters; kill the writeEn when writeAddr is x0

src/src/common/bundles/RfAccessInfoNdPort.scala

@@ -5,9 +5,9 @@ import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
 import chisel3.util._
 import spec._
 
-class RfAccessInfoNdPort extends Bundle {
+class RfAccessInfoNdPort(addrWidth: internal.firrtl.Width = Width.Reg.addr) extends Bundle {
   val en   = Bool()
-  val addr = UInt(Width.Reg.addr)
+  val addr = UInt(addrWidth)
 }
 
 object RfAccessInfoNdPort {

src/src/frontend/BiInstQueue.scala

@@ -81,7 +81,7 @@ class BiInstQueue(
   io.dequeuePorts(1).valid := !isEmptyByOne
 
   // enqueue
-  val numWidth: Int = log2Ceil(issueNum)
+  // val numWidth: Int = log2Ceil(issueNum)
 
   val enqEn = (io.enqueuePorts.map(port => (port.ready && port.valid)))
   // val enqueueNum = io.enqueuePorts.map(_.valid).map(_.asUInt).reduce(_ + _)

src/src/pipeline/README.md

@@ -1,3 +1,6 @@
+# 发射设计
+双发射：顺序发射+（伪）乱序执行+顺序写回 (未实现寄存器重命名，无法解决RAW造成的阻塞浪费)
+
 # 线路复用情况
 
 1. decode info for exeState

src/src/pipeline/dispatch/BiIssueStage.scala

@@ -15,6 +15,7 @@ import pipeline.dataforward.bundles.ReadPortWithValid
 import pipeline.dispatch.bundles.IssueInfoWithValidBundle
 import pipeline.rob.bundles.RobIdDistributePort
 
+// TODO: deal WAR data hazard
 class BiIssueStage(
   issueNum:       Int = 2,
   scoreChangeNum: Int = Param.regFileWriteNum,
@@ -62,21 +63,19 @@ class BiIssueStage(
   io.issuedInfoPorts := issueInfosReg
 
   // fall back
-  if (true) {
-    io.fetchInstDecodePorts.foreach { port =>
-      port.ready := false.B
-    }
-    io.occupyPortss.foreach(_.foreach { port =>
-      port.en   := false.B
-      port.addr := zeroWord
-    })
-    io.csrOccupyPortss.foreach(_.foreach { port =>
-      port.en   := false.B
-      port.addr := zeroWord
-    })
-    io.issuedInfoPorts.foreach(_ := IssuedInfoNdPort.default)
-    io.instInfoPorts.foreach(_ := InstInfoNdPort.default)
+  io.fetchInstDecodePorts.foreach { port =>
+    port.ready := false.B
   }
+  io.occupyPortss.foreach(_.foreach { port =>
+    port.en   := false.B
+    port.addr := zeroWord
+  })
+  io.csrOccupyPortss.foreach(_.foreach { port =>
+    port.en   := false.B
+    port.addr := zeroWord
+  })
+  io.issuedInfoPorts.foreach(_ := IssuedInfoNdPort.default)
+  io.instInfoPorts.foreach(_ := InstInfoNdPort.default)
 
   /** Combine stage 1 : get fetch infos
     */

src/src/pipeline/dispatch/Rename.scala

@@ -0,0 +1,215 @@
+package pipeline.dispatch
+
+import chisel3._
+import chisel3.util._
+import pipeline.dispatch.bundles.ScoreboardChangeNdPort
+import spec._
+import pipeline.dispatch.enums.{PrfState => State}
+import pipeline.dispatch.bundles.RenameRequestNdPort
+import pipeline.dispatch.bundles.RenameResultNdPort
+import utils.BiPriorityMux
+import utils.BiCounter
+import control.bundles.PipelineControlNDPort
+
+// 重命名+计分板，仅供乱序发射使用,顺序发射时不需要
+class Rename(
+  arfRegNum: Int = Count.reg,
+  prfRegNum: Int = 64,
+  changeNum: Int = Param.scoreboardChangeNum,
+  occupyNum: Int = Param.regFileWriteNum,
+  renameNum: Int = 2)
+    extends Module {
+
+  val arfNumLog: Int = log2Ceil(arfRegNum)
+  val prfNumLog: Int = log2Ceil(prfRegNum)
+  val io = IO(new Bundle {
+    val commitPorts = Input(Vec(changeNum, new ScoreboardChangeNdPort(prfNumLog.W)))
+    val freePorts   = Input(Vec(changeNum, new ScoreboardChangeNdPort(prfNumLog.W)))
+    val regScores   = Output(Vec(prfRegNum, State()))
+
+    val renameRequestPorts = Input(Vec(renameNum, new RenameRequestNdPort))
+    val renameResultPorts  = Output(Vec(renameNum, new RenameResultNdPort))
+
+    val pipelineControlPort = Input(new PipelineControlNDPort)
+  })
+
+  require(renameNum == 2)
+
+  io <> DontCare
+
+  /** State Transform
+    *
+    * free ---rename request write------------> busy
+    *
+    * busy ---------write back----------------> retire
+    *
+    * retire --next prf ( -> same arf) commit--> empty
+    */
+
+  val arfToPrfMap = RegInit(VecInit(Seq.range(0, arfRegNum).map(_.U(prfNumLog.W))))
+
+  val prfPrevMap = RegInit(VecInit(Seq.fill(prfRegNum)(0.U(prfNumLog.W))))
+
+  val prfStateReg = RegInit(VecInit(Seq.range(0, prfRegNum).map { index =>
+    if (index < arfRegNum) {
+      State.retire
+    } else {
+      State.free
+    }
+  }))
+
+  io.regScores.zip(prfStateReg).foreach {
+    case (dst, src) =>
+      dst := src
+  }
+
+  /** free queue
+    */
+
+  val freeQueueLength = prfRegNum - arfRegNum
+  val freeQueue = RegInit(
+    VecInit(
+      Seq.range(arfRegNum, prfRegNum).map {
+        _.U(prfNumLog.W)
+      }
+    )
+  )
+
+  val enq_ptr = Module(new BiCounter(freeQueueLength))
+  val deq_ptr = Module(new BiCounter(freeQueueLength))
+  enq_ptr.io.inc   := 0.U
+  enq_ptr.io.flush := io.pipelineControlPort.flush
+  deq_ptr.io.inc   := 0.U
+  deq_ptr.io.flush := io.pipelineControlPort.flush
+
+  val maybeFull = RegInit(true.B)
+  val ptrMatch  = enq_ptr.io.value === deq_ptr.io.value
+  val isEmpty   = ptrMatch && !maybeFull
+  val isFull    = ptrMatch && maybeFull
+
+  val storeNum = WireDefault(
+    Mux(
+      enq_ptr.io.value > deq_ptr.io.value,
+      enq_ptr.io.value - deq_ptr.io.value,
+      (freeQueueLength.U - deq_ptr.io.value) + enq_ptr.io.value
+    )
+  )
+  val emptyNum = WireDefault(freeQueueLength.U - storeNum)
+
+  val isEmptyByOne = WireDefault(storeNum === 1.U)
+  val isFullByOne  = WireDefault(emptyNum === 1.U)
+
+  /** Rename Request From RenameStage
+    *
+    * free --> busy
+    */
+
+  val deqRequest = WireDefault(VecInit(io.renameRequestPorts.map { port =>
+    (port.arfWritePort.en && port.arfWritePort.addr.orR)
+  }))
+  val deqNum = WireDefault(deqRequest.map(_.asUInt).reduce(_ +& _))
+
+  io.renameResultPorts.zip(io.renameRequestPorts).foreach {
+    case (dst, src) =>
+      dst.grfReadPorts.zip(src.arfReadPorts).foreach {
+        case (dstRead, srcRead) =>
+          dstRead.en   := srcRead.en
+          dstRead.addr := arfToPrfMap(srcRead.addr)
+      }
+  }
+
+  when(!isEmpty) {
+    // 至少可重命名1个
+    when(deqRequest(0)) {
+      deq_ptr.io.inc                          := 1.U
+      io.renameResultPorts(0).grfWritePort.en := true.B
+
+      val renameAddr = WireDefault(freeQueue(deq_ptr.io.value))
+      io.renameResultPorts(0).grfWritePort.addr := renameAddr
+
+      prfPrevMap(renameAddr) := arfToPrfMap(
+        io.renameRequestPorts(0).arfWritePort.addr
+      )
+      arfToPrfMap(io.renameRequestPorts(0).arfWritePort.addr) := renameAddr
+
+      prfStateReg(renameAddr) := State.busy
+
+      // 覆盖1的写重命名
+      io.renameResultPorts.zip(io.renameRequestPorts).foreach {
+        case (dst, src) =>
+          dst.grfReadPorts.zip(src.arfReadPorts).foreach {
+            case (dstRead, srcRead) =>
+              dstRead.en := srcRead.en
+          }
+      }
+
+      io.renameRequestPorts(1)
+        .arfReadPorts
+        .zip(io.renameResultPorts(1).grfReadPorts)
+        .foreach {
+          case (dstRead, srcRead) =>
+            when(srcRead.addr === io.renameRequestPorts(0).arfWritePort.addr) {
+              dstRead.addr := renameAddr
+            }
+        }
+
+      when(deqRequest(1) && !isEmptyByOne) {
+        // 重命名2个
+        deq_ptr.io.inc                          := 2.U
+        io.renameResultPorts(1).grfWritePort.en := true.B
+
+        val renameAddr2 = WireDefault(freeQueue(deq_ptr.io.value + 1.U))
+        io.renameResultPorts(1).grfWritePort.addr               := renameAddr2
+        prfStateReg(renameAddr2)                                := State.busy
+        arfToPrfMap(io.renameRequestPorts(1).arfWritePort.addr) := renameAddr2
+        when(
+          io.renameRequestPorts(1).arfWritePort.addr =/= io.renameRequestPorts(0).arfWritePort.addr
+        ) {
+          prfPrevMap(renameAddr2) := arfToPrfMap(
+            io.renameRequestPorts(1).arfWritePort.addr
+          )
+        }.otherwise {
+          // write the same reg
+          prfPrevMap(renameAddr2) := renameAddr
+        }
+
+      }
+
+    }.elsewhen(deqRequest(1)) {
+      deq_ptr.io.inc                          := 1.U
+      io.renameResultPorts(1).grfWritePort.en := true.B
+
+      val renameAddr = WireDefault(freeQueue(deq_ptr.io.value))
+      io.renameResultPorts(1).grfWritePort.addr := renameAddr
+
+      prfPrevMap(renameAddr) := arfToPrfMap(
+        io.renameRequestPorts(1).arfWritePort.addr
+      )
+      arfToPrfMap(io.renameRequestPorts(1).arfWritePort.addr) := renameAddr
+
+      prfStateReg(renameAddr) := State.busy
+    }
+  }
+
+  /** Rename - Retire From WbStage
+    *
+    * busy --> retire
+    */
+
+  io.freePorts.foreach { port =>
+    when(port.en) {
+      prfStateReg(port.addr) := State.retire
+    }
+  }
+
+  /** Rename - Next Commit From Rob
+    *
+    * retire -> empty
+    */
+
+  io.commitPorts.foreach { port =>
+    when(port.en) {
+      prfStateReg(prfPrevMap(port.addr)) := State.free
+    }
+  }
+}

src/src/pipeline/dispatch/bundles/RenameRequestNdPort.scala

@@ -0,0 +1,12 @@
+package pipeline.dispatch.bundles
+
+import chisel3._
+import common.bundles.RfAccessInfoNdPort
+
+class RenameRequestNdPort(
+  regReadNum:   Int                   = 2,
+  arfAddrWidth: internal.firrtl.Width = 5.W)
+    extends Bundle {
+  val arfWritePort = new RfAccessInfoNdPort(arfAddrWidth)
+  val arfReadPorts = Vec(regReadNum, new RfAccessInfoNdPort(arfAddrWidth))
+}

src/src/pipeline/dispatch/bundles/RenameResultNdPort.scala

@@ -0,0 +1,20 @@
+package pipeline.dispatch.bundles
+
+import chisel3._
+import common.bundles.RfAccessInfoNdPort
+import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
+
+class RenameResultNdPort(
+  regReadNum:   Int                   = 2,
+  grfAddrWidth: internal.firrtl.Width = 6.W)
+    extends Bundle {
+  val grfWritePort = new RfAccessInfoNdPort(grfAddrWidth)
+  val grfReadPorts = Vec(regReadNum, new RfAccessInfoNdPort(grfAddrWidth))
+}
+
+object RenameResultNdPort {
+  def setDefault(port: RenameResultNdPort) {
+    port.grfWritePort := RfAccessInfoNdPort.default
+    port.grfReadPorts.foreach(_ := RfAccessInfoNdPort.default)
+  }
+}

src/src/pipeline/dispatch/bundles/ScoreboardChangeNdPort.scala

@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import spec._
 
-class ScoreboardChangeNdPort extends Bundle {
+class ScoreboardChangeNdPort(addrWidth: internal.firrtl.Width = Width.Reg.addr) extends Bundle {
   val en   = Bool()
-  val addr = UInt(Width.Reg.addr)
+  val addr = UInt(addrWidth)
 }

src/src/pipeline/dispatch/decode/Decoder_2R.scala

@@ -9,15 +9,16 @@ import pipeline.dispatch.bundles.DecodeOutNdPort
 class Decoder_2R extends Decoder {
   io.out := DecodeOutNdPort.default
 
-  val opcode = WireDefault(io.instInfoPort.inst(31, 10))
-  val rj     = WireDefault(io.instInfoPort.inst(9, 5))
-  val rd     = WireDefault(io.instInfoPort.inst(4, 0))
+  val opcode      = WireDefault(io.instInfoPort.inst(31, 10))
+  val rj          = WireDefault(io.instInfoPort.inst(9, 5))
+  val rd          = WireDefault(io.instInfoPort.inst(4, 0))
+  val rdIsNotZero = WireDefault(rd.orR)
 
   io.out.info.isHasImm := false.B
 
   switch(io.instInfoPort.inst) {
     is(Inst.rdcnt_id_vl) {
-      io.out.info.gprWritePort.en := true.B
+      io.out.info.gprWritePort.en := rdIsNotZero
       when(rd.orR) {
         io.out.info.gprWritePort.addr := rj
         io.out.info.exeOp             := ExeInst.Op.rdcntid
@@ -27,7 +28,7 @@ class Decoder_2R extends Decoder {
       }
     }
     is(Inst.rdcnt_vh) {
-      io.out.info.gprWritePort.en   := true.B
+      io.out.info.gprWritePort.en   := rdIsNotZero
       io.out.info.gprWritePort.addr := rd
       io.out.info.exeOp             := ExeInst.Op.rdcntvh_w
     }

src/src/pipeline/dispatch/decode/Decoder_2RI12.scala

@@ -10,10 +10,11 @@ import pipeline.dispatch.bundles.DecodeOutNdPort
 class Decoder_2RI12 extends Decoder {
   io.out := DecodeOutNdPort.default
 
-  val opcode = WireDefault(io.instInfoPort.inst(31, 22))
-  val imm12  = WireDefault(io.instInfoPort.inst(21, 10))
-  val rj     = WireDefault(io.instInfoPort.inst(9, 5))
-  val rd     = WireDefault(io.instInfoPort.inst(4, 0))
+  val opcode      = WireDefault(io.instInfoPort.inst(31, 22))
+  val imm12       = WireDefault(io.instInfoPort.inst(21, 10))
+  val rj          = WireDefault(io.instInfoPort.inst(9, 5))
+  val rd          = WireDefault(io.instInfoPort.inst(4, 0))
+  val rdIsNotZero = WireDefault(rd.orR)
 
   def outInfo = io.out.info
 
@@ -32,7 +33,7 @@ class Decoder_2RI12 extends Decoder {
   io.out.info.gprReadPorts(0).addr := rj
   io.out.info.gprReadPorts(1).en   := false.B
   io.out.info.gprReadPorts(1).addr := DontCare
-  io.out.info.gprWritePort.en      := true.B
+  io.out.info.gprWritePort.en      := rdIsNotZero // true.B
   io.out.info.gprWritePort.addr    := rd
 
   // Fallback