Mem stage port

src/src/memory/enums/ReadWriteSel.scala → src/src/common/enums/ReadWriteSel.scala

@@ -1,4 +1,4 @@
-package memory.enums
+package common.enums
 
 import chisel3.ChiselEnum
 

src/src/memory/DCache.scala

@@ -5,8 +5,9 @@ import axi.bundles.AxiMasterPort
 import chisel3._
 import chisel3.util._
 import chisel3.util.random.LFSR
+import common.enums.ReadWriteSel
 import memory.bundles.{DCacheAccessPort, StatusTagBundle}
-import memory.enums.{DCacheState => State, ReadWriteSel}
+import memory.enums.{DCacheState => State}
 import spec._
 
 class DCache(

src/src/memory/bundles/DCacheAccessPort.scala

@@ -1,7 +1,7 @@
 package memory.bundles
 
 import chisel3._
-import memory.enums.ReadWriteSel
+import common.enums.ReadWriteSel
 import spec._
 
 class DCacheAccessPort extends Bundle {

src/src/pipeline/mem/MemStage.scala

@@ -3,14 +3,9 @@ package pipeline.mem
 import chisel3._
 import chisel3.util._
 import common.bundles.{PassThroughPort, RfWriteNdPort}
-import pipeline.dispatch.bundles.ExeInstNdPort
-import spec.ExeInst.Sel
-import spec._
 import pipeline.execution.bundles.MemLoadStoreInfoNdPort
-import chisel3.experimental.VecLiterals._
-import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
 import control.bundles.PipelineControlNDPort
-import pipeline.mem.bundles.MemLoadStorePort
+import pipeline.mem.bundles.MemAccessNdPort
 import pipeline.writeback.bundles.InstInfoNdPort
 import pipeline.dispatch.bundles.ScoreboardChangeNdPort
 
@@ -23,14 +18,13 @@ class MemStage extends Module {
     // `Cu` -> `MemStage`
     val pipelineControlPort = Input(new PipelineControlNDPort)
     // `MemStage` -> Cu
-    val stallRequest = Output(Bool())
-    // `MemStage` -> ?Ram
-    val memLoadStorePort = Flipped(new MemLoadStorePort)
+    val stallRequest     = Output(Bool())
+    val memLoadStorePort = Flipped(new MemAccessNdPort)
 
     // Scoreboard
     val freePorts = Output(new ScoreboardChangeNdPort)
 
-    // (next clock pause)
+    // (Next clock pulse)
     val instInfoPassThroughPort = new PassThroughPort(new InstInfoNdPort)
   })
 
@@ -49,16 +43,9 @@ class MemStage extends Module {
 
   io.stallRequest := false.B
 
-  val storeData = WireDefault(io.memLoadStoreInfoPort.data)
-  val hint      = WireDefault(io.memLoadStoreInfoPort.data)
-
   io.memLoadStorePort <> DontCare
 
-  // Indicate the availability in scoreboard
-  io.freePorts.en   := false.B
-  io.freePorts.addr := io.gprWritePassThroughPort.out.addr
-
-  // flush or clear
+  // Flush or clear
   when(io.pipelineControlPort.flush || io.pipelineControlPort.clear) {
     gprWriteReg := RfWriteNdPort.default
     InstInfoNdPort.setDefault(instInfoReg)

src/src/pipeline/mem/bundles/MemAccessNdPort.scala

@@ -0,0 +1,18 @@
+package pipeline.mem.bundles
+
+import chisel3._
+import chisel3.util._
+import spec._
+import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
+import common.enums.ReadWriteSel
+
+class MemAccessNdPort extends Bundle {
+  val isValid  = Bool()
+  val isAtomic = Bool()
+  val rw       = ReadWriteSel
+  val addr     = UInt(Width.Reg.data)
+  val write = new Bundle {
+    val mask = UInt(Width.Reg.data)
+    val data = UInt(Width.Reg.data)
+  }
+}

src/src/pipeline/writeback/bundles/InstInfoNdPort.scala

@@ -28,5 +28,4 @@ object InstInfoNdPort {
     instInfoPort.csrWritePort := CsrWriteNdPort.default
     instInfoPort.exeOp        := 0.U
   }
-
 }

src/src/spec/Param.scala

@@ -29,8 +29,6 @@ object Param {
     val exeOp                 = 8.W
     val simpleFetchStageState = 2.W
 
-    val memSel = 4.W
-
     object Axi { // crossbar
       val slaveId  = 8
       val masterId = slaveId + log2Ceil(Count.Axi.slave)

src/test/src/DCacheSpec.scala

@@ -2,9 +2,9 @@ import chiseltest._
 import utest._
 import chisel3._
 import chisel3.util._
+import common.enums.ReadWriteSel
 import memory.DCache
 import memory.bundles.StatusTagBundle
-import memory.enums.ReadWriteSel
 import spec.Param
 
 import scala.collection.immutable