(CAN MERGE)remove data forward temporily; feat: add BiInstQueue, BiIssueStage, RobStage; add memAccessPort in ExeStage

src/src/CoreCpuTop.scala

@@ -111,7 +111,7 @@ class CoreCpuTop extends Module {
   val scoreboard    = Module(new Scoreboard)
   val csrScoreBoard = Module(new Scoreboard(changeNum = Param.csrScoreBoardChangeNum, regNum = Count.csrReg))
 
-  val dataforward = Module(new DataForwardStage)
+  // val dataforward = Module(new DataForwardStage)
 
   val regFile = Module(new RegFile)
   val pc      = Module(new Pc)
@@ -131,9 +131,8 @@ class CoreCpuTop extends Module {
   // Pc
   pc.io.newPc := cu.io.newPc
 
-
   // TODO: debug crossbar
-  io.axi <> simpleFetchStage.io.axiMasterInterface
+  io.axi      <> simpleFetchStage.io.axiMasterInterface
   crossbar.io <> DontCare
 //  // AXI top <> AXI crossbar
 //  crossbar.io.slaves                       <> DontCare
@@ -231,9 +230,10 @@ class CoreCpuTop extends Module {
   issueStage.io.csrRegScores               := csrScoreBoard.io.regScores
   csrScoreBoard.io.occupyPorts             := issueStage.io.csrOccupyPorts
 
-  scoreboard.io.freePorts(0)    := exeStage.io.freePorts
-  scoreboard.io.freePorts(1)    := memStage.io.freePorts
-  scoreboard.io.freePorts(2)    := wbStage.io.freePorts(0)
+  // scoreboard.io.freePorts(0)    := exeStage.io.freePorts
+  // scoreboard.io.freePorts(1)    := memStage.io.freePorts
+  // scoreboard.io.freePorts(2)    := wbStage.io.freePorts(0)
+  scoreboard.io.freePorts(0)    := wbStage.io.freePorts(0)
   csrScoreBoard.io.freePorts(0) := wbStage.io.csrFreePorts(0)
 
   // Reg-read stage
@@ -242,9 +242,9 @@ class CoreCpuTop extends Module {
   regReadStage.io.gprReadPorts(1)            <> regFile.io.readPorts(1)
   regReadStage.io.pipelineControlPort        := cu.io.pipelineControlPorts(PipelineStageIndex.regReadStage)
   regReadStage.io.instInfoPassThroughPort.in := issueStage.io.instInfoPassThroughPort.out
-  regReadStage.io.dataforwardPorts.zip(dataforward.io.readPorts).foreach {
-    case (regRead, df) => regRead <> df
-  }
+  // regReadStage.io.dataforwardPorts.zip(dataforward.io.readPorts).foreach {
+  //   case (regRead, df) => regRead <> df
+  // }
 
   // Execution stage
   exeStage.io.exeInstPort                := regReadStage.io.exeInstPort
@@ -253,8 +253,8 @@ class CoreCpuTop extends Module {
 
   // Mem stage
   memStage.io.gprWritePassThroughPort.in := exeStage.io.gprWritePort
-  memStage.io.memLoadStoreInfoPort       := exeStage.io.memLoadStoreInfoPort // TODO: MemLoadStoreInfoPort is deprecated
-  memStage.io.pipelineControlPort        := cu.io.pipelineControlPorts(PipelineStageIndex.memStage)
+  // memStage.io.memLoadStoreInfoPort       := exeStage.io.memLoadStoreInfoPort // TODO: MemLoadStoreInfoPort is deprecated
+  // memStage.io.pipelineControlPort        := //cu.io.pipelineControlPorts(PipelineStageIndex.memStage)
   memStage.io.memAccessPort              <> DontCare
   memStage.io.instInfoPassThroughPort.in := exeStage.io.instInfoPassThroughPort.out
 
@@ -264,13 +264,13 @@ class CoreCpuTop extends Module {
   regFile.io.writePort                  := cu.io.gprWritePassThroughPorts.out(0)
 
   // data forward
-  dataforward.io.writePorts(0) := exeStage.io.gprWritePort
-  dataforward.io.writePorts(1) := memStage.io.gprWritePassThroughPort.out
+  // dataforward.io.writePorts(0) := exeStage.io.gprWritePort
+  // dataforward.io.writePorts(1) := memStage.io.gprWritePassThroughPort.out
 
   // Ctrl unit
   cu.io.instInfoPorts(0)               := wbStage.io.instInfoPassThroughPort.out
   cu.io.exeStallRequest                := exeStage.io.stallRequest
-  cu.io.memStallRequest                := memStage.io.stallRequest
+  cu.io.memStallRequest                := false.B // memStage.io.stallRequest    *********** TODO
   cu.io.gprWritePassThroughPorts.in(0) := wbStage.io.gprWritePort
   cu.io.csrValues                      := csr.io.csrValues
   cu.io.stableCounterReadPort          <> stableCounter.io

src/src/axi/AxiCrossbarRead.scala

@@ -282,7 +282,7 @@ class AxiCrossbarRead(
     val slaveAruserMux   = WireInit(IntSlavesAr(aGrantEncoded).user)
     val slaveArvalidMux  = WireInit(IntArValid(aGrantEncoded)(index) && aGrantValid)
     val slaveArreadyMux  = Wire(Bool())
-    slaveAridMux     := IntSlavesAr(aGrantEncoded).id | (aGrantEncoded << Param.Width.Axi.slaveId).asUInt
+    slaveAridMux := IntSlavesAr(aGrantEncoded).id | (aGrantEncoded << Param.Width.Axi.slaveId).asUInt
 
     IntArReady(index) := (aGrantValid && slaveArreadyMux) << aGrantEncoded
 

src/src/common/Pc.scala

@@ -14,7 +14,7 @@ class Pc(
   val io = IO(new Bundle {
     val pc     = Output(UInt(Width.Reg.data))
     val isNext = Input(Bool())
-    // 异常处理
+    // 异常处理 + 分支跳转
     val newPc = Input(new PcSetPort)
   })
 

src/src/frontend/BiInstQueue.scala

@@ -0,0 +1,211 @@
+package frontend
+
+import chisel3._
+import chisel3.util._
+
+import spec._
+import pipeline.dispatch.bundles.InstInfoBundle
+import control.bundles.PipelineControlNDPort
+import frontend._
+import pipeline.dispatch.bundles.{DecodeOutNdPort, DecodePort, InstInfoBundle, IssuedInfoNdPort, ScoreboardChangeNdPort}
+import pipeline.dispatch.decode.{
+  Decoder,
+  Decoder_2R,
+  Decoder_2RI12,
+  Decoder_2RI14,
+  Decoder_2RI16,
+  Decoder_3R,
+  Decoder_4R,
+  Decoder_special
+}
+import pipeline.writeback.bundles.InstInfoNdPort
+import utils.BiCounter
+// 尝试写双发射的queue，未接入，不用管它
+// assert: enqueuePorts总是最低的几位有效
+class BiInstQueue(
+  val queueLength: Int = Param.instQueueLength,
+  val issueNum:    Int = Param.issueInstInfoMaxNum)
+    extends Module {
+  val io = IO(new Bundle {
+    // val isFlush     = Input(Bool())
+    val pipelineControlPort = Input(new PipelineControlNDPort)
+    val enqueuePorts        = Vec(issueNum, Flipped(Decoupled(new InstInfoBundle)))
+
+    // `InstQueue` -> `IssueStage`
+    val dequeuePorts = Vec(
+      issueNum,
+      Decoupled(new Bundle {
+        val decode   = new DecodeOutNdPort
+        val instInfo = new InstInfoNdPort
+      })
+    )
+
+    // val debugPort = Output(Vec(issueNum, new InstInfoBundle))
+  })
+  require(issueNum == 2)
+//   val queue =
+//     Queue(io.enqueuePorts(0), entries = queueLength, pipe = false, flow = true, flush = Some(io.pipelineControlPort.flush))
+
+//   io.dequeuePort <> queue
+
+  val ram     = RegInit(VecInit(Seq.fill(queueLength)(InstInfoBundle.default)))
+  val enq_ptr = Module(new BiCounter(queueLength))
+  val deq_ptr = Module(new BiCounter(queueLength))
+
+  enq_ptr.io.inc   := 0.U
+  enq_ptr.io.flush := io.pipelineControlPort.flush
+  deq_ptr.io.inc   := 0.U
+  deq_ptr.io.flush := io.pipelineControlPort.flush
+
+  val maybeFull = RegInit(false.B)
+  val ptrMatch  = enq_ptr.io.value === deq_ptr.io.value
+  val isEmpty   = ptrMatch && !maybeFull
+  val isFull    = ptrMatch && maybeFull
+
+  val storeNum = WireDefault(
+    Mux(
+      enq_ptr.io.value > deq_ptr.io.value,
+      enq_ptr.io.value - deq_ptr.io.value,
+      (queueLength.U - deq_ptr.io.value) + enq_ptr.io.value
+    )
+  )
+  val emptyNum = WireDefault(queueLength.U - storeNum)
+
+  val isEmptyByOne = WireDefault(storeNum === 1.U)
+  val isFullByOne  = WireDefault(emptyNum === 1.U)
+
+  io.enqueuePorts(0).ready := !isFull
+  io.enqueuePorts(1).ready := !isFullByOne
+
+  io.dequeuePorts(0).valid := !isEmpty
+  io.dequeuePorts(1).valid := !isEmptyByOne
+
+  // enqueue
+  val numWidth: Int = log2Ceil(issueNum)
+
+  val enqEn = (io.enqueuePorts.map(port => (port.ready && port.valid)))
+  // val enqueueNum = io.enqueuePorts.map(_.valid).map(_.asUInt).reduce(_ + _)
+  // 优化
+  val enqueueNum = Cat(
+    enqEn(0) & enqEn(1),
+    enqEn(0) ^ enqEn(1)
+  )
+
+  // dequeue
+  val deqEn = (io.dequeuePorts.map(port => (port.ready && port.valid)))
+  // val dequeueNum = io.dequeuePorts.map(_.valid).map(_.asUInt).reduce(_ + _)
+  val dequeueNum = Cat(
+    deqEn(0) & deqEn(1),
+    deqEn(0) ^ deqEn(1)
+  )
+
+  when(enqueueNum > dequeueNum) {
+    maybeFull := true.B
+  }.elsewhen(enqueueNum < dequeueNum) {
+    maybeFull := false.B
+  }
+
+  when(!isFull) {
+    when(enqueueNum(1)) {
+      // 请求入队两个
+      ram(enq_ptr.io.value) := io.enqueuePorts(0).bits
+      when(isFullByOne) {
+        // 只剩一个位置
+        enq_ptr.io.inc := 1.U
+      }.otherwise {
+        // 直接加两个
+        ram(enq_ptr.io.value + 1.U) := io.enqueuePorts(1).bits
+        enq_ptr.io.inc              := 2.U
+      }
+    }.elsewhen(enqueueNum(0)) {
+      // 请求入队一个
+      ram(enq_ptr.io.value) := io.enqueuePorts(0).bits
+      enq_ptr.io.inc        := 1.U
+    }
+  }
+
+  when(!isEmpty) {
+    when(dequeueNum(1)) {
+      // 请求出队两个
+      when(isEmptyByOne) {
+        // 只有一条指令
+        deq_ptr.io.inc := 1.U
+      }.otherwise {
+        // 正常出队两条
+        deq_ptr.io.inc := 2.U
+      }
+    }.elsewhen(dequeueNum(0)) {
+      // 请求出队一个
+      deq_ptr.io.inc := 1.U
+    }
+  }
+  // Decode
+
+  val decodeInstInfos = WireDefault(VecInit(ram(deq_ptr.io.value), ram(deq_ptr.io.value + 1.U)))
+
+  // io.debugPort(0) := decodeInstInfos(0)
+  // io.debugPort(1) := decodeInstInfos(1)
+
+  // Select a decoder
+
+  val decoders0 = Seq(
+    Module(new Decoder_2RI12),
+    Module(new Decoder_2RI14),
+    Module(new Decoder_2RI16),
+    Module(new Decoder_2R),
+    Module(new Decoder_3R),
+    // Module(new Decoder_4R),
+    Module(new Decoder_special)
+  )
+
+  val decoders1 = Seq(
+    Module(new Decoder_2RI12),
+    Module(new Decoder_2RI14),
+    Module(new Decoder_2RI16),
+    Module(new Decoder_2R),
+    Module(new Decoder_3R),
+    // Module(new Decoder_4R),
+    Module(new Decoder_special)
+  )
+
+  decoders0.foreach(_.io.instInfoPort := decodeInstInfos(0))
+  decoders1.foreach(_.io.instInfoPort := decodeInstInfos(1))
+
+  val decoderWires = Wire(Vec(2, Vec(decoders0.length, new DecodeOutNdPort)))
+  // decoderWires.zip(decoders).foreach {
+  //   case (port, decoder) =>
+  //     port := decoder.io.out
+  // }
+  decoderWires.zip(Seq(decoders0, decoders1)).foreach {
+    case (decoderWire, decoders) =>
+      decoderWire.zip(decoders).foreach {
+        case (port, decoder) =>
+          port := decoder.io.out
+      }
+  }
+
+  // val decoderIndex    = WireDefault(OHToUInt(Cat(decoderWires.map(_.isMatched).reverse)))
+  // val selectedDecoder = WireDefault(decoderWires(decoderIndex))
+  val decoderIndices = WireDefault(VecInit(decoderWires.map { decoderWire =>
+    OHToUInt(Cat(decoderWire.map(_.isMatched).reverse))
+  }))
+  val selectedDecoders = WireDefault(VecInit(decoderWires.zip(decoderIndices).map {
+    case (decoderWire, decoderIndex) =>
+      decoderWire(decoderIndex)
+  }))
+
+  io.dequeuePorts.lazyZip(selectedDecoders).lazyZip(decodeInstInfos).zipWithIndex.foreach {
+    case ((dequeuePort, selectedDecoder, decodeInstInfo), index) =>
+      dequeuePort.bits.decode := selectedDecoder
+      // InstInfoNdPort.setDefault(dequeuePort.bits.instInfo)
+      dequeuePort.bits.instInfo      := InstInfoNdPort.default
+      dequeuePort.bits.instInfo.pc   := decodeInstInfo.pcAddr
+      dequeuePort.bits.instInfo.inst := decodeInstInfo.inst
+      dequeuePort.bits.instInfo
+        .exceptionRecords(CsrRegs.ExceptionIndex.ine) := !decoderWires(index).map(_.isMatched).reduce(_ || _)
+  }
+
+  when(io.pipelineControlPort.flush) {
+    ram.foreach(_ := InstInfoBundle.default)
+  }
+}

src/src/frontend/InstQueue.scala

@@ -84,13 +84,17 @@ class InstQueue(val queueLength: Int = Param.instQueueLength) extends Module {
     case (port, decoder) =>
       port := decoder.io.out
   }
+
+  val isMatched       = WireDefault(decoderWires.map(_.isMatched).reduce(_ || _))
   val decoderIndex    = WireDefault(OHToUInt(Cat(decoderWires.map(_.isMatched).reverse)))
   val selectedDecoder = WireDefault(decoderWires(decoderIndex))
 
   io.dequeuePort.bits.decode := selectedDecoder
-  InstInfoNdPort.setDefault(io.dequeuePort.bits.instInfo)
-  io.dequeuePort.bits.instInfo.pc   := decodeInstInfo.pcAddr
-  io.dequeuePort.bits.instInfo.inst := decodeInstInfo.inst
+  // InstInfoNdPort.setDefault(io.dequeuePort.bits.instInfo)
+  io.dequeuePort.bits.instInfo                                              := InstInfoNdPort.default
+  io.dequeuePort.bits.instInfo.exceptionRecords(CsrRegs.ExceptionIndex.ine) := !isMatched
+  io.dequeuePort.bits.instInfo.pc                                           := decodeInstInfo.pcAddr
+  io.dequeuePort.bits.instInfo.inst                                         := decodeInstInfo.inst
 
   // io.dequeuePort <> queue
 

src/src/memory/bundles/MemAccessNdPort.scala

@@ -2,15 +2,27 @@ package memory.bundles
 
 import chisel3._
 import common.enums.ReadWriteSel
+import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
 import spec._
 
 class MemAccessNdPort extends Bundle {
-  val isValid = Bool()
-  val rw      = ReadWriteSel
-  val addr    = UInt(Width.Reg.data)
+  val isValid    = Bool()
+  val rw         = ReadWriteSel()
+  val addr       = UInt(Width.Reg.data)
+  val isUnsigned = Bool()
 
   val write = new Bundle {
-    val data = UInt(Width.Reg.data)
-    val mask = UInt(Width.Reg.data)
+    val data = UInt(Width.Mem.data)
+    val mask = UInt((Width.Mem._data / byteLength).W)
   }
 }
+
+object MemAccessNdPort {
+  val default = (new MemAccessNdPort).Lit(
+    _.isValid -> false.B,
+    _.rw -> ReadWriteSel.read,
+    _.addr -> zeroWord,
+    _.write.data -> zeroWord,
+    _.write.mask -> zeroWord
+  )
+}

src/src/pipeline/dataforward/DataForwardStage.scala

@@ -7,13 +7,14 @@ import common.bundles.RfWriteNdPort
 import common.bundles.RfReadPort
 import pipeline.dataforward.bundles._
 
+import pipeline.dataforward.bundles.ReadPortWithValid
 class DataForwardStage(
   dataForwardNum: Int = Param.dataForwardInputNum,
   readNum:        Int = Param.regFileReadNum)
     extends Module {
   val io = IO(new Bundle {
     val writePorts = Input(Vec(dataForwardNum, new RfWriteNdPort))
-    val readPorts  = Vec(readNum, new DataForwardReadPort)
+    val readPorts  = Vec(readNum, new ReadPortWithValid)
   })
 
   io.readPorts.foreach { readPort =>

src/src/pipeline/dataforward/bundles/DataForwardReadPort.scala → src/src/pipeline/dataforward/bundles/ReadPortWithValid.scala

@@ -4,7 +4,7 @@ import chisel3._
 import common.bundles.RfReadPort
 import spec._
 
-class DataForwardReadPort extends Bundle {
+class ReadPortWithValid extends Bundle {
   val en    = Input(Bool())
   val addr  = Input(UInt(Width.Reg.addr))
   val valid = Output(Bool())