feat: add many many many CsrRegs ; delect divisorZeroException

src/src/CoreCpuTop.scala

@@ -239,14 +239,14 @@ class CoreCpuTop extends Module {
   // Write-back stage
   wbStage.io.gprWriteInfoPort           := memStage.io.gprWritePassThroughPort.out
   wbStage.io.instInfoPassThroughPort.in := memStage.io.instInfoPassThroughPort.out
-  regFile.io.writePort                  := cu.io.gprWritePassThroughPort.out
+  regFile.io.writePort                  := cu.io.gprWritePassThroughPorts.out(0)
   scoreboard.io.freePorts               := wbStage.io.freePorts
 
   // Ctrl unit
-  cu.io.instInfoPort               := wbStage.io.instInfoPassThroughPort.out
-  cu.io.exeStallRequest            := exeStage.io.stallRequest
-  cu.io.memStallRequest            := memStage.io.stallRequest
-  cu.io.gprWritePassThroughPort.in := wbStage.io.gprWritePort
+  cu.io.instInfoPorts(0)               := wbStage.io.instInfoPassThroughPort.out
+  cu.io.exeStallRequest                := exeStage.io.stallRequest
+  cu.io.memStallRequest                := memStage.io.stallRequest
+  cu.io.gprWritePassThroughPorts.in(0) := wbStage.io.gprWritePort
 
   // Csr
   csr.io.writePorts.zip(cu.io.csrWritePorts).foreach {

src/src/pipeline/ctrl/Csr.scala

@@ -6,24 +6,127 @@ import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
 import spec._
 import pipeline.ctrl.bundles.PipelineControlNDPort
 import spec.PipelineStageIndex
-import pipeline.ctrl.bundles.CsrWriteNdPort
+import pipeline.ctrl.bundles._
+import pipeline.ctrl.bundles.EentryBundle
+import pipeline.ctrl.bundles.TlbehiBundle
 
 class Csr(writeNum: Int = Param.csrRegsWriteNum) extends Module {
   val io = IO(new Bundle {
     val writePorts = Input(Vec(writeNum, new CsrWriteNdPort))
     val csrValues  = Output(Vec(Count.csrReg, UInt(Width.Reg.data)))
   })
 
+  // Util: view UInt as Bundle
+  class BundlePassPort[T <: Bundle](port: T) extends Bundle {
+    val in  = Wire(port)
+    val out = Wire(port)
+  }
+
+  def viewUInt[T <: Bundle](u: UInt, bun: T): BundlePassPort[T] = {
+    val passPort = new BundlePassPort(bun)
+    u            := passPort.in.asUInt
+    passPort.out := u.asTypeOf(bun)
+    passPort
+  }
+
   val csrRegs = RegInit(VecInit(Seq.fill(Count.csrReg)(zeroWord)))
 
   io.writePorts.foreach { writePort =>
     when(writePort.en) {
       csrRegs(writePort.addr) := writePort.data
       // 保留域
       switch(writePort.addr) {
+        is(CsrRegs.Index.crmd) {
+          csrRegs(writePort.addr) := Cat(0.U(23.W), writePort.data(8, 0))
+        }
+        is(CsrRegs.Index.prmd) {
+          csrRegs(writePort.addr) := Cat(0.U(29.W), writePort.data(2, 0))
+        }
+        is(CsrRegs.Index.euen) {
+          csrRegs(writePort.addr) := Cat(0.U(31.W), writePort.data(0))
+        }
+        is(CsrRegs.Index.ecfg) {
+          csrRegs(writePort.addr) := Cat(0.U(19.W), writePort.data(12, 0))
+        }
         is(CsrRegs.Index.estat) {
           csrRegs(writePort.addr) := Cat(false.B, writePort.data(30, 16), 0.U(3.W), writePort.data(12, 0))
         }
+        is(
+          CsrRegs.Index.era,
+          CsrRegs.Index.badv,
+          CsrRegs.Index.save0,
+          CsrRegs.Index.save1,
+          CsrRegs.Index.save2,
+          CsrRegs.Index.save3,
+          CsrRegs.Index.tid
+        ) {
+          csrRegs(writePort.addr) := writePort.data
+        }
+        is(CsrRegs.Index.eentry) {
+          csrRegs(writePort.addr) := Cat(writePort.data(31, 6), 0.U(6.W))
+        }
+        is(CsrRegs.Index.cpuid) {
+          csrRegs(writePort.addr) := Cat(0.U(23.W), writePort.data(8, 0))
+        }
+        is(CsrRegs.Index.llbctl) {
+          csrRegs(writePort.addr) := Cat(0.U(29.W), writePort.data(2, 0))
+        }
+        is(CsrRegs.Index.tlbidx) {
+          csrRegs(writePort.addr) := Cat(
+            writePort.data(31),
+            false.B,
+            writePort.data(29, 24),
+            0.U((24 - CsrRegs.Tlbidx.Width.index).W),
+            writePort.data(CsrRegs.Tlbidx.Width.index - 1, 0)
+          )
+        }
+        is(CsrRegs.Index.tlbehi) {
+          csrRegs(writePort.addr) := Cat(writePort.data(31, 13), 0.U(13.W))
+        }
+        is(CsrRegs.Index.tlbelo0, CsrRegs.Index.tlbelo1) {
+          csrRegs(writePort.addr) := Cat(
+            writePort.data(31, 8),
+            false.B,
+            writePort.data(6, 0)
+          )
+        }
+        is(CsrRegs.Index.asid) {
+          csrRegs(writePort.addr) := Cat(
+            0.U(8.W),
+            writePort.data(23, 16),
+            0.U(6.W),
+            writePort.data(9, 0)
+          )
+        }
+        is(CsrRegs.Index.pgdl, CsrRegs.Index.pgdh, CsrRegs.Index.pgd) {
+          csrRegs(writePort.addr) := Cat(writePort.data(31, 12), 0.U(12.W))
+        }
+        is(CsrRegs.Index.tlbrentry) {
+          csrRegs(writePort.addr) := Cat(writePort.data(31, 6), 0.U(6.W))
+        }
+        is(CsrRegs.Index.dmw0, CsrRegs.Index.dmw1) {
+          csrRegs(writePort.addr) := Cat(
+            writePort.data(31, 29),
+            false.B,
+            writePort.data(27, 25),
+            0.U(19.W),
+            writePort.data(5, 3),
+            0.U(2.W),
+            writePort.data(0)
+          )
+        }
+        is(CsrRegs.Index.tcfg, CsrRegs.Index.tval) {
+          csrRegs(writePort.addr) := Cat(
+            0.U((32 - CsrRegs.TimeVal.Width.timeVal).W),
+            writePort.data(CsrRegs.TimeVal.Width.timeVal - 1, 0)
+          )
+        }
+        is(CsrRegs.Index.ticlr) {
+          csrRegs(writePort.addr) := Cat(
+            0.U(31.W),
+            writePort.data(0)
+          )
+        }
       }
     }
   }
@@ -33,12 +136,109 @@ class Csr(writeNum: Int = Param.csrRegsWriteNum) extends Module {
       output := reg
   }
 
+  // CRMD 当前模式信息
+
+  val crmd = viewUInt(csrRegs(CsrRegs.Index.crmd), new CrmdBundle)
+  crmd.in := CrmdBundle.default
+
+  // PRMD 例外前模式信息
+  val prmd = viewUInt(csrRegs(CsrRegs.Index.prmd), new PrmdBundle)
+  prmd.in := PrmdBundle.default
+
+  // EUEN扩展部件使能
+  val euen = viewUInt(csrRegs(CsrRegs.Index.euen), new EuenBundle)
+  euen.in := EuenBundle.default
+
+  // ECFG 例外控制
+  val ecfg = viewUInt(csrRegs(CsrRegs.Index.ecfg), new EcfgBundle)
+  ecfg.in := EcfgBundle.default
+
   // ESTAT
-  val estatRegValue = WireDefault(csrRegs(CsrRegs.Index.estat))
-  val estat = new Bundle {
-    val is       = estatRegValue(12, 0)
-    val ecode    = estatRegValue(21, 16)
-    val esubcode = estatRegValue(30, 22)
+  val estat = viewUInt(csrRegs(CsrRegs.Index.estat), new EstatBundle)
+  estat.in := EstatBundle.default
+
+  // ERA 例外返回地址
+  val era = viewUInt(csrRegs(CsrRegs.Index.era), new EraBundle)
+  era.in := EraBundle.default
+
+  // BADV 出错虚地址
+  val badv = viewUInt(csrRegs(CsrRegs.Index.badv), new BadvBundle)
+  badv.in := BadvBundle.default
+
+  // EENTRY 例外入口地址
+  val eentry = viewUInt(csrRegs(CsrRegs.Index.eentry), new EentryBundle)
+  eentry.in := EentryBundle.default
+
+  // CPUID 处理器编号
+  val cpuid = viewUInt(csrRegs(CsrRegs.Index.cpuid), new CpuidBundle)
+  cpuid.in := CpuidBundle.default
+
+  // SAVE0-3 数据保存
+  val saves = VecInit(CsrRegs.Index.save0, CsrRegs.Index.save1, CsrRegs.Index.save2, CsrRegs.Index.save3).map { idx =>
+    viewUInt(csrRegs(idx), new CsrSaveBundle)
   }
+  saves.foreach { save => save.in := CsrSaveBundle.default }
+
+  // LLBCTL  LLBit控制
+  val llbctl = viewUInt(csrRegs(CsrRegs.Index.llbctl), new LlbctlBundle)
+  llbctl.in := LlbctlBundle.default
+
+  // TLBIDX  TLB索引
+  val tlbidx = viewUInt(csrRegs(CsrRegs.Index.tlbidx), new TlbidxBundle)
+  tlbidx.in := TlbidxBundle.default
+
+  // TLBEHI  TLB表项高位
+  val tlbehi = viewUInt(csrRegs(CsrRegs.Index.tlbehi), new TlbehiBundle)
+  tlbehi.in := TlbehiBundle.default
+
+  // TLBELO 0-1  TLB表项低位
+  val tlbelo0 = viewUInt(csrRegs(CsrRegs.Index.tlbelo0), new TlbeloBundle)
+  tlbelo0.in := TlbeloBundle.default
+
+  val tlbelo1 = viewUInt(csrRegs(CsrRegs.Index.tlbelo1), new TlbeloBundle)
+  tlbelo1.in := TlbeloBundle.default
+
+  // ASID 地址空间标识符
+  val asid = viewUInt(csrRegs(CsrRegs.Index.asid), new AsidBundle)
+  asid.in := AsidBundle.default
+
+  // PGDL 低半地址空间全局目录基址
+  val pgdl = viewUInt(csrRegs(CsrRegs.Index.pgdl), new PgdlBundle)
+  pgdl.in := PgdlBundle.default
+
+  // PGDH 高半地址空间全局目录基址
+  val pgdh = viewUInt(csrRegs(CsrRegs.Index.pgdh), new PgdhBundle)
+  pgdh.in := PgdhBundle.default
+
+  // PGD 全局地址空间全局目录基址
+  val pgd = viewUInt(csrRegs(CsrRegs.Index.pgd), new PgdBundle)
+  pgd.in := PgdBundle.default
+
+  // TLBRENTRY  TLB重填例外入口地址
+  val tlbrentry = viewUInt(csrRegs(CsrRegs.Index.tlbrentry), new TlbrentryBundle)
+  tlbrentry.in := TlbrentryBundle.default
+
+  // DMW 0-1 直接映射配置窗口
+  val dmw0 = viewUInt(csrRegs(CsrRegs.Index.dmw0), new DmwBundle)
+  dmw0.in := DmwBundle.default
+
+  val dmw1 = viewUInt(csrRegs(CsrRegs.Index.dmw1), new DmwBundle)
+  dmw1.in := DmwBundle.default
+
+  // TID 定时器编号
+  val tid = viewUInt(csrRegs(CsrRegs.Index.tid), new TidBundle)
+  tid.in := TidBundle.default
+
+  // TCFG 定时器配置
+  val tcfg = viewUInt(csrRegs(CsrRegs.Index.tcfg), new TcfgBundle)
+  tcfg.in := TcfgBundle.default
+
+  // TVAL 定时器数值
+  val tval = viewUInt(csrRegs(CsrRegs.Index.tval), new TvalBundle)
+  tval.in := TvalBundle.default
+
+  // TICLR 定时器中断清除
+  val ticlr = viewUInt(csrRegs(CsrRegs.Index.ticlr), new TiclrBundle)
+  ticlr.in := TiclrBundle.default
 
 }

src/src/pipeline/ctrl/Cu.scala

@@ -14,11 +14,15 @@ import pipeline.ctrl.bundles.CsrWriteNdPort
 // TODO: Add stall to frontend ?
 // TODO: Add flush to stages
 // TODO: Add deal exceptions
-class Cu(ctrlControlNum: Int = Param.ctrlControlNum, writeNum: Int = Param.csrRegsWriteNum) extends Module {
+class Cu(
+  ctrlControlNum: Int = Param.ctrlControlNum,
+  writeNum:       Int = Param.csrRegsWriteNum,
+  dispatchNum:    Int = Param.dispatchInstNum)
+    extends Module {
   val io = IO(new Bundle {
     // `WbStage` -> `Cu`
-    val gprWritePassThroughPort = new PassThroughPort(new RfWriteNdPort)
-    val instInfoPort            = Input(new InstInfoNdPort)
+    val gprWritePassThroughPorts = new PassThroughPort(Vec(dispatchNum, new RfWriteNdPort))
+    val instInfoPorts            = Input(Vec(dispatchNum, new InstInfoNdPort))
     // `Cu` -> `Csr`
     val csrWritePorts = Output(Vec(writeNum, new CsrWriteNdPort))
     // `ExeStage` -> `Cu`
@@ -29,32 +33,57 @@ class Cu(ctrlControlNum: Int = Param.ctrlControlNum, writeNum: Int = Param.csrRe
     val pipelineControlPorts = Output(Vec(ctrlControlNum, new PipelineControlNDPort))
   })
 
-  // TODO: Finish correct connection
-  io.csrWritePorts := DontCare
-
-  /** Stall
+  /** Stall 暂停流水线前面部分
     */
 
   io.pipelineControlPorts.foreach(_ := PipelineControlNDPort.default)
-  // `ExeStage` --stall--> `IssueStage`, `RegReadStage` (DONT STALL ITSELF)
-  Seq(PipelineStageIndex.issueStage, PipelineStageIndex.regReadStage)
+  // `ExeStage` --stall--> `IssueStage`, `RegReadStage`, `ExeStage` (STALL ITSELF)
+  Seq(PipelineStageIndex.issueStage, PipelineStageIndex.regReadStage, PipelineStageIndex.exeStage)
     .map(io.pipelineControlPorts(_))
     .foreach(_.stall := io.exeStallRequest)
-  // `MemStage` --stall--> `IssueStage`, `RegReadStage`, `ExeStage`  (DONT STALL ITSELF)
-  Seq(PipelineStageIndex.issueStage, PipelineStageIndex.regReadStage, PipelineStageIndex.exeStage)
+  // `MemStage` --stall--> `IssueStage`, `RegReadStage`, `ExeStage`, `MemStage`  (STALL ITSELF)
+  Seq(
+    PipelineStageIndex.issueStage,
+    PipelineStageIndex.regReadStage,
+    PipelineStageIndex.exeStage,
+    PipelineStageIndex.memStage
+  )
     .map(io.pipelineControlPorts(_))
     .foreach(_.stall := io.memStallRequest)
 
+  /** clear
+    *
+    * Assume A -> B, A is stall but B is not stall. Give A a clear signal to clear its output
+    */
+
+  Seq(
+    PipelineStageIndex.issueStage,
+    PipelineStageIndex.regReadStage,
+    PipelineStageIndex.exeStage,
+    PipelineStageIndex.memStage
+  ).map(io.pipelineControlPorts(_)).reduce { (prev, next) =>
+    prev.clear := prev.stall && !next.stall
+    next
+  }
+
   /** Exception
     */
-  val hasException = WireDefault(io.instInfoPort.exceptionRecords.reduce(_ || _))
+  val hasException = WireDefault(io.instInfoPorts.map(_.exceptionRecords.reduce(_ || _)).reduce(_ || _))
 
   /** Write Regfile
     */
   // temp
-  io.gprWritePassThroughPort.out := Mux(
+  io.gprWritePassThroughPorts.out(0) := Mux(
     hasException,
-    io.gprWritePassThroughPort.in,
+    io.gprWritePassThroughPorts.in(0),
     RfWriteNdPort.default
   )
+
+  io.csrWritePorts.foreach { port => port := CsrWriteNdPort.default }
+
+  /** flush
+    */
+
+  val flush = WireDefault(hasException)
+  io.pipelineControlPorts.foreach(_.flush := flush)
 }

src/src/pipeline/ctrl/bundles/AsidBundle.scala

@@ -0,0 +1,16 @@
+package pipeline.ctrl.bundles
+
+import chisel3._
+import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
+import spec._
+
+class AsidBundle extends Bundle {
+  val zero1    = UInt(8.W)
+  val asidbits = UInt(8.W)
+  val zero2    = UInt(6.W)
+  val asid     = UInt(10.W)
+}
+
+object AsidBundle {
+  val default = 0.U.asTypeOf(new AsidBundle)
+}

src/src/pipeline/ctrl/bundles/BadvBundle.scala

@@ -0,0 +1,13 @@
+package pipeline.ctrl.bundles
+
+import chisel3._
+import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
+import spec._
+
+class BadvBundle extends Bundle {
+  val vaddr = UInt(Width.Reg.data)
+}
+
+object BadvBundle {
+  val default = 0.U.asTypeOf(new BadvBundle)
+}

src/src/pipeline/ctrl/bundles/CpuidBundle.scala

@@ -0,0 +1,14 @@
+package pipeline.ctrl.bundles
+
+import chisel3._
+import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
+import spec._
+
+class CpuidBundle extends Bundle {
+  val zero   = UInt(23.W)
+  val coreId = UInt(9.W)
+}
+
+object CpuidBundle {
+  val default = 0.U.asTypeOf(new CpuidBundle)
+}