refactor: rename MemLoadStoreNdPort -> MemLoadStoreInfoNdPort

src/src/CoreCpuTop.scala

@@ -159,8 +159,9 @@ class CoreCpuTop extends Module {
 
   // Mem stage
   memStage.io.gprWritePassThroughPort.in := exeStage.io.gprWritePort
-  memStage.io.memLoadStorePort           := exeStage.io.memLoadStorePort
+  memStage.io.memLoadStoreInfoPort       := exeStage.io.memLoadStoreInfoPort
   memStage.io.pipelineControlPort        := cu.io.pipelineControlPorts(PipelineStageIndex.memStage)
+  memStage.io.memLoadStorePort           <> DontCare
   memStage.io.wbDebugPassthroughPort.in  := exeStage.io.wbDebugPassthroughPort.out
 
   // Write-back stage

src/src/pipeline/execution/ExeStage.scala

@@ -7,7 +7,7 @@ import pipeline.dispatch.bundles.ExeInstNdPort
 import spec.ExeInst.Sel
 import spec._
 import pipeline.ctrl.bundles.PipelineControlNDPort
-import pipeline.execution.bundles.MemLoadStoreNdPort
+import pipeline.execution.bundles.MemLoadStoreInfoNdPort
 import chisel3.experimental.VecLiterals._
 import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
 import spec.Param.{ExeStageState => State}
@@ -20,8 +20,8 @@ class ExeStage(readNum: Int = Param.instRegReadNum) extends Module {
 
     // TODO: Add `MemStage` in between
     // `ExeStage` -> `WbStage` (next clock pulse)
+    val memLoadStoreInfoPort = Output(new MemLoadStoreInfoNdPort)
     val gprWritePort           = Output(new RfWriteNdPort)
-    val memLoadStorePort       = Output(new MemLoadStoreNdPort)
     val wbDebugPassthroughPort = new PassThroughPort(new WbDebugNdPort)
 
     // Pipeline control signal
@@ -119,9 +119,9 @@ class ExeStage(readNum: Int = Param.instRegReadNum) extends Module {
   }
 
   // MemLoadStore
-  io.memLoadStorePort.exeOp := io.exeInstPort.exeOp
+  io.memLoadStoreInfoPort.exeOp := io.exeInstPort.exeOp
   // store : the data to write
   // preld, dbar, ibar : hint
-  io.memLoadStorePort.data  := io.exeInstPort.rightOperand
-  io.memLoadStorePort.vaddr := (io.exeInstPort.leftOperand + io.exeInstPort.loadStoreImm)
+  io.memLoadStoreInfoPort.data  := io.exeInstPort.rightOperand
+  io.memLoadStoreInfoPort.vaddr := (io.exeInstPort.leftOperand + io.exeInstPort.loadStoreImm)
 }

src/src/pipeline/execution/bundles/MemLoadStoreNdPort.scala → src/src/pipeline/execution/bundles/MemLoadStoreInfoNdPort.scala

@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import spec._
 
-class MemLoadStoreNdPort extends Bundle {
+class MemLoadStoreInfoNdPort extends Bundle {
   val exeOp = UInt(Param.Width.exeOp)
   val vaddr = UInt(Width.Reg.data)
   val data  = UInt(Width.Reg.data)

src/src/pipeline/mem/MemStage.scala

@@ -7,22 +7,25 @@ import pipeline.dispatch.bundles.ExeInstNdPort
 import spec.ExeInst.Sel
 import spec._
 import pipeline.ctrl.bundles.PipelineControlNDPort
-import pipeline.execution.bundles.MemLoadStoreNdPort
+import pipeline.execution.bundles.MemLoadStoreInfoNdPort
 import chisel3.experimental.VecLiterals._
 import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
+import pipeline.mem.bundles.MemLoadStorePort
 import pipeline.writeback.bundles.WbDebugNdPort
 
 class MemStage extends Module {
   val io = IO(new Bundle {
     // `ExeStage` -> `MemStage` -> `WbStage`
     val gprWritePassThroughPort = new PassThroughPort(new RfWriteNdPort)
     // `ExeStage` -> `MemStage`
-    val memLoadStorePort = Input(new MemLoadStoreNdPort)
+    val memLoadStoreInfoPort = Input(new MemLoadStoreInfoNdPort)
     // `Cu` -> `MemStage`
     val pipelineControlPort = Input(new PipelineControlNDPort)
     // `MemStage` -> Cu
     val stallRequest = Output(Bool())
-
+    // `MemStage` -> ?Ram
+    val memLoadStorePort = Flipped(new MemLoadStorePort)
+
     val wbDebugPassthroughPort = new PassThroughPort(new WbDebugNdPort)
   })
 
@@ -39,4 +42,9 @@ class MemStage extends Module {
   io.gprWritePassThroughPort.out := gprWriteReg
 
   io.stallRequest := false.B
+
+  val storeData = WireDefault(io.memLoadStoreInfoPort.data)
+  val hint      = WireDefault(io.memLoadStoreInfoPort.data)
+
+  io.memLoadStorePort <> DontCare
 }

src/src/pipeline/mem/bundles/MemLoadStorePort.scala

@@ -0,0 +1,15 @@
+package pipeline.mem.bundles
+
+import chisel3._
+import chisel3.util._
+import spec._
+import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
+
+class MemLoadStorePort extends Bundle {
+  val valid     = Input(Bool())
+  val mode      = Input(Bool())
+  val memSel    = Input(UInt(Param.Width.memSel))
+  val addr      = Input(UInt(Width.Reg.data))
+  val dataWrite = Input(UInt(Width.Reg.data))
+  val dataRead  = Output(UInt(Width.Reg.data))
+}

src/src/spec/Param.scala

@@ -21,6 +21,8 @@ object Param {
     val exeOp                 = 8.W
     val simpleFetchStageState = 2.W
 
+    val memSel = 4.W
+
     object Axi { // crossbar
       val slaveId  = 8
       val masterId = slaveId + log2Ceil(Count.Axi.slave)

src/src/spec/package.scala

@@ -31,6 +31,11 @@ package object spec {
     def getCount: Int = count
   }
 
+  object ReadWriteMode {
+    val read  = false.B
+    val write = true.B
+  }
+
   object Width {
     val inst = wordLength.W
     object Reg {