Connect difftest csr_rstat

src/src/CoreCpuTop.scala

@@ -296,7 +296,6 @@ class CoreCpuTop extends Module {
       t.cmt_wdest        := w.wdest
       t.cmt_wdata        := w.wdata
       t.cmt_csr_rstat_en := w.csr_rstat
-      t.cmt_csr_data     := w.csr_data
       t.cmt_inst_ld_en   := w.ld_en
       t.cmt_ld_vaddr     := w.ld_vaddr
       t.cmt_ld_paddr     := w.ld_paddr
@@ -347,6 +346,7 @@ class CoreCpuTop extends Module {
       t.csr_pgdh_diff_0      := c.pgdh.asUInt
 
       t.cmt_csr_ecode := c.estat.ecode
+      t.cmt_csr_data  := c.estat.asUInt
     case _ =>
   }
 }

src/src/control/Csr.scala

@@ -337,8 +337,8 @@ class Csr(
 
   // estat
   when(io.csrMessage.exceptionFlush) {
-    estat.in.ecode    := io.csrMessage.ecodeBunle.ecode
-    estat.in.esubcode := io.csrMessage.ecodeBunle.esubcode
+    estat.in.ecode    := io.csrMessage.ecodeBundle.ecode
+    estat.in.esubcode := io.csrMessage.ecodeBundle.esubcode
   }
 
   // era

src/src/control/Cu.scala

@@ -129,52 +129,52 @@ class Cu(
     io.csrMessage.era := selectInstInfo.pc
     switch(selectException) {
       is(Csr.ExceptionIndex.int) {
-        io.csrMessage.ecodeBunle := Csr.Estat.int
+        io.csrMessage.ecodeBundle := Csr.Estat.int
       }
       is(Csr.ExceptionIndex.pil) {
-        io.csrMessage.ecodeBunle := Csr.Estat.pil
+        io.csrMessage.ecodeBundle := Csr.Estat.pil
       }
       is(Csr.ExceptionIndex.pis) {
-        io.csrMessage.ecodeBunle := Csr.Estat.pis
+        io.csrMessage.ecodeBundle := Csr.Estat.pis
       }
       is(Csr.ExceptionIndex.pif) {
-        io.csrMessage.ecodeBunle := Csr.Estat.pif
+        io.csrMessage.ecodeBundle := Csr.Estat.pif
       }
       is(Csr.ExceptionIndex.pme) {
-        io.csrMessage.ecodeBunle := Csr.Estat.pme
+        io.csrMessage.ecodeBundle := Csr.Estat.pme
       }
       is(Csr.ExceptionIndex.ppi) {
-        io.csrMessage.ecodeBunle := Csr.Estat.ppi
+        io.csrMessage.ecodeBundle := Csr.Estat.ppi
       }
       is(Csr.ExceptionIndex.adef) {
-        io.csrMessage.ecodeBunle := Csr.Estat.adef
+        io.csrMessage.ecodeBundle := Csr.Estat.adef
       }
       is(Csr.ExceptionIndex.adem) {
-        io.csrMessage.ecodeBunle := Csr.Estat.adem
+        io.csrMessage.ecodeBundle := Csr.Estat.adem
       }
       is(Csr.ExceptionIndex.ale) {
-        io.csrMessage.ecodeBunle := Csr.Estat.ale
+        io.csrMessage.ecodeBundle := Csr.Estat.ale
       }
       is(Csr.ExceptionIndex.sys) {
-        io.csrMessage.ecodeBunle := Csr.Estat.sys
+        io.csrMessage.ecodeBundle := Csr.Estat.sys
       }
       is(Csr.ExceptionIndex.brk) {
-        io.csrMessage.ecodeBunle := Csr.Estat.brk
+        io.csrMessage.ecodeBundle := Csr.Estat.brk
       }
       is(Csr.ExceptionIndex.ine) {
-        io.csrMessage.ecodeBunle := Csr.Estat.ine
+        io.csrMessage.ecodeBundle := Csr.Estat.ine
       }
       is(Csr.ExceptionIndex.ipe) {
-        io.csrMessage.ecodeBunle := Csr.Estat.ipe
+        io.csrMessage.ecodeBundle := Csr.Estat.ipe
       }
       is(Csr.ExceptionIndex.fpd) {
-        io.csrMessage.ecodeBunle := Csr.Estat.fpd
+        io.csrMessage.ecodeBundle := Csr.Estat.fpd
       }
       is(Csr.ExceptionIndex.fpe) {
-        io.csrMessage.ecodeBunle := Csr.Estat.fpe
+        io.csrMessage.ecodeBundle := Csr.Estat.fpe
       }
       is(Csr.ExceptionIndex.tlbr) {
-        io.csrMessage.ecodeBunle := Csr.Estat.tlbr
+        io.csrMessage.ecodeBundle := Csr.Estat.tlbr
       }
     }
   }

src/src/control/bundles/CuToCsrNdPort.scala

@@ -8,7 +8,7 @@ class CuToCsrNdPort extends Bundle {
   val exceptionFlush = Bool()
   val ertnFlush      = Bool()
   val era            = UInt(Width.Reg.data)
-  val ecodeBunle     = new EcodeBundle
+  val ecodeBundle    = new EcodeBundle
   // tlb重填失效
   val tlbRefillException = Bool()
   // 出错虚地址

src/src/pipeline/writeback/WbStage.scala

@@ -45,7 +45,6 @@ class WbStage extends Module {
           val wdest          = UInt(Width.Reg.addr)
           val wdata          = UInt(Width.Reg.data)
           val csr_rstat      = Bool()
-          val csr_data       = UInt(Width.Reg.data)
           val ld_en          = UInt(8.W)
           val ld_vaddr       = UInt(32.W)
           val ld_paddr       = UInt(32.W)
@@ -79,22 +78,24 @@ class WbStage extends Module {
   val exceptionVec = io.in.bits.instInfo.exceptionRecords
   io.difftest match {
     case Some(dt) =>
-      dt           := DontCare
-      dt.valid     := RegNext(io.in.bits.instInfo.isValid && io.in.valid)
-      dt.pc        := RegNext(io.in.bits.instInfo.pc)
-      dt.instr     := RegNext(io.in.bits.instInfo.inst)
-      dt.wen       := RegNext(io.in.bits.gprWrite.en)
-      dt.wdest     := RegNext(io.in.bits.gprWrite.addr)
-      dt.wdata     := RegNext(io.in.bits.gprWrite.data)
-      dt.csr_rstat := RegNext(io.in.bits.instInfo.csrWritePort.en)
-      dt.csr_data  := RegNext(io.in.bits.instInfo.csrWritePort.data)
-      dt.ld_en     := RegNext(io.in.bits.instInfo.load.en)
-      dt.ld_vaddr  := RegNext(io.in.bits.instInfo.load.vaddr)
-      dt.ld_paddr  := RegNext(io.in.bits.instInfo.load.paddr)
-      dt.st_en     := RegNext(io.in.bits.instInfo.store.en)
-      dt.st_vaddr  := RegNext(io.in.bits.instInfo.store.vaddr)
-      dt.st_paddr  := RegNext(io.in.bits.instInfo.store.paddr)
-      dt.st_data   := RegNext(io.in.bits.instInfo.store.data)
+      dt       := DontCare
+      dt.valid := RegNext(io.in.bits.instInfo.isValid && io.in.valid)
+      dt.pc    := RegNext(io.in.bits.instInfo.pc)
+      dt.instr := RegNext(io.in.bits.instInfo.inst)
+      dt.wen   := RegNext(io.in.bits.gprWrite.en)
+      dt.wdest := RegNext(io.in.bits.gprWrite.addr)
+      dt.wdata := RegNext(io.in.bits.gprWrite.data)
+      dt.csr_rstat := RegNext(
+        io.in.bits.instInfo.inst(31, 24) === Inst._2RI14.csr_ &&
+          io.in.bits.instInfo.inst(23, 10) === "h5".U
+      )
+      dt.ld_en    := RegNext(io.in.bits.instInfo.load.en)
+      dt.ld_vaddr := RegNext(io.in.bits.instInfo.load.vaddr)
+      dt.ld_paddr := RegNext(io.in.bits.instInfo.load.paddr)
+      dt.st_en    := RegNext(io.in.bits.instInfo.store.en)
+      dt.st_vaddr := RegNext(io.in.bits.instInfo.store.vaddr)
+      dt.st_paddr := RegNext(io.in.bits.instInfo.store.paddr)
+      dt.st_data  := RegNext(io.in.bits.instInfo.store.data)
     case _ =>
   }
 }

src/src/spec/Csr.scala

@@ -42,7 +42,7 @@ object Csr {
     "98",
     "180",
     "181"
-  ).map(h(_))
+  ).map(h)
 
   object Index {
     var count = -1