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feat: tune params #110

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Merged
rewired-gh merged 5 commits into from
May 31, 2023
Merged

feat: tune params #110

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b042143
feat: tune params
May 31, 2023
fe379f9
fix: scoreboard change timing
May 31, 2023
6957197
Revert "fix: scoreboard change timing"
May 31, 2023
830902c
fix: scoreboard change timing
May 31, 2023
7c3cfd5
feat: use MFC
May 31, 2023
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2 changes: 1 addition & 1 deletion src/src/Elaborate.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ import circt.stage.{CIRCTTarget, CIRCTTargetAnnotation}
import pipeline.dispatch.BiIssueStage

object Elaborate extends App {
val useMFC = false // Use MLIR-based firrtl compiler
val useMFC = true // Use MLIR-based firrtl compiler
val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
def top = new CoreCpuTop

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6 changes: 3 additions & 3 deletions src/src/pipeline/dispatch/Scoreboard.scala
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Expand Up @@ -32,12 +32,12 @@ class Scoreboard(
// GPR 0 is not meant to be written and always keeps 0
reg := State.free
} else {
when(io.occupyPorts.map(port => port.en && port.addr === index.U).reduce(_ || _)) {
reg := State.beforeMem
}.elsewhen(io.freePorts.map(port => port.en && port.addr === index.U).reduce(_ || _)) {
when(io.freePorts.map(port => port.en && port.addr === index.U).reduce(_ || _)) {
reg := State.free
}.elsewhen(io.toMemPorts.map(port => port.en && port.addr === index.U).reduce(_ || _)) {
reg := State.inMem
}.elsewhen(io.occupyPorts.map(port => port.en && port.addr === index.U).reduce(_ || _)) {
reg := State.beforeMem
}
}
}
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10 changes: 5 additions & 5 deletions src/src/spec/Param.scala
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Expand Up @@ -8,7 +8,7 @@ object Param {

val isDiffTest = true

val instQueueLength = 5
val instQueueLength = 8
val regFileReadNum = 2
val regFileWriteNum = 1
val scoreboardChangeNum = 1 // 3
Expand Down Expand Up @@ -43,7 +43,7 @@ object Param {
}

object DCache {
val _addr = 6 // TODO: Choose an optimal value
val _addr = 8 // TODO: Choose an optimal value
val _byteOffset = log2Ceil(Count.DCache.dataPerLine) + log2Ceil(wordLength / byteLength)
val _dataLine = Count.DCache.dataPerLine * spec.Width.Mem._data
val _tag = spec.Width.Mem._addr - _addr - _byteOffset
Expand All @@ -55,7 +55,7 @@ object Param {
}

object ICache {
val _addr = 6 // TODO: Choose an optimal value
val _addr = 8 // TODO: Choose an optimal value
val _byteOffset = log2Ceil(Count.ICache.dataPerLine) + log2Ceil(wordLength / byteLength)
val _dataLine = Count.ICache.dataPerLine * spec.Width.Mem._data
val _tag = spec.Width.Mem._addr - _addr - _byteOffset
Expand All @@ -75,13 +75,13 @@ object Param {

object DCache {
val setLen = 2 // Also the number of RAMs for data; TODO: Choose an optimal value
val dataPerLine = 4 // TODO: One data line is 64 bytes
val dataPerLine = 16 // TODO: One data line is 64 bytes
val sizePerRam = math.pow(2, Width.DCache._addr).toInt
}

object ICache {
val setLen = 2 // Also the number of RAMs for data; TODO: Choose an optimal value
val dataPerLine = 4 // TODO: One data line is 64 bytes
val dataPerLine = 16 // TODO: One data line is 64 bytes
val sizePerRam = math.pow(2, Width.ICache._addr).toInt
}

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