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Merge tag 'mfd-next-4.14' of git://git.kernel.org/pub/scm/linux/kerne…
…l/git/lee/mfd
Pull MFD updates from Lee Jones:
"New Drivers
- RK805 Power Management IC (PMIC)
- ROHM BD9571MWV-M MFD Power Management IC (PMIC)
- Texas Instruments TPS68470 Power Management IC (PMIC) & LEDs
New Device Support:
- Add support for HiSilicon Hi6421v530 to hi6421-pmic-core
- Add support for X-Powers AXP806 to axp20x
- Add support for X-Powers AXP813 to axp20x
- Add support for Intel Sunrise Point LPSS to intel-lpss-pci
New Functionality:
- Amend API to provide register layout; atmel-smc
Fix-ups:
- DT re-work; omap, nokia
- Header file location change {I2C => MFD}; dm355evm_msp, tps65010
- Fix chip ID formatting issue(s); rk808
- Optionally register touchscreen devices; da9052-core
- Documentation improvements; twl-core
- Constification; rtsx_pcr, ab8500-core, da9055-i2c, da9052-spi
- Drop unnecessary static declaration; max8925-i2c
- Kconfig changes (missing deps and remove module support)
- Slim down oversized licence statement; hi6421-pmic-core
- Use managed resources (devm_*); lp87565
- Supply proper error checking/handling; t7l66xb
Bug Fixes:
- Fix counter duplication issue; da9052-core
- Fix potential NULL deference issue; max8998
- Leave SPI-NOR write-protection bit alone; lpc_ich
- Ensure device is put into reset during suspend; intel-lpss
- Correct register offset variable size; omap-usb-tll"
* tag 'mfd-next-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (61 commits)
mfd: intel_soc_pmic: Differentiate between Bay and Cherry Trail CRC variants
mfd: intel_soc_pmic: Export separate mfd-cell configs for BYT and CHT
dt-bindings: mfd: Add bindings for ZII RAVE devices
mfd: omap-usb-tll: Fix register offsets
mfd: da9052: Constify spi_device_id
mfd: intel-lpss: Put I2C and SPI controllers into reset state on suspend
mfd: da9055: Constify i2c_device_id
mfd: intel-lpss: Add missing PCI ID for Intel Sunrise Point LPSS devices
mfd: t7l66xb: Handle return value of clk_prepare_enable
mfd: Add ROHM BD9571MWV-M PMIC DT bindings
mfd: intel_soc_pmic_chtwc: Turn Kconfig option into a bool
mfd: lp87565: Convert to use devm_mfd_add_devices()
mfd: Add support for TPS68470 device
mfd: lpc_ich: Do not touch SPI-NOR write protection bit on Haswell/Broadwell
mfd: syscon: atmel-smc: Add helper to retrieve register layout
mfd: axp20x: Use correct platform device ID for many PEK
dt-bindings: mfd: axp20x: Introduce bindings for AXP813
mfd: axp20x: Add support for AXP813 PMIC
dt-bindings: mfd: axp20x: Add AXP806 to supported list of chips
mfd: Add ROHM BD9571MWV-M MFD PMIC driver
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,57 @@ | ||
| What: /sys/bus/iio/devices/iio:deviceX/in_count0_preset | ||
| KernelVersion: 4.13 | ||
| Contact: fabrice.gasnier@st.com | ||
| Description: | ||
| Reading returns the current preset value. Writing sets the | ||
| preset value. Encoder counts continuously from 0 to preset | ||
| value, depending on direction (up/down). | ||
|
|
||
| What: /sys/bus/iio/devices/iio:deviceX/in_count_quadrature_mode_available | ||
| KernelVersion: 4.13 | ||
| Contact: fabrice.gasnier@st.com | ||
| Description: | ||
| Reading returns the list possible quadrature modes. | ||
|
|
||
| What: /sys/bus/iio/devices/iio:deviceX/in_count0_quadrature_mode | ||
| KernelVersion: 4.13 | ||
| Contact: fabrice.gasnier@st.com | ||
| Description: | ||
| Configure the device counter quadrature modes: | ||
| - non-quadrature: | ||
| Encoder IN1 input servers as the count input (up | ||
| direction). | ||
| - quadrature: | ||
| Encoder IN1 and IN2 inputs are mixed to get direction | ||
| and count. | ||
|
|
||
| What: /sys/bus/iio/devices/iio:deviceX/in_count_polarity_available | ||
| KernelVersion: 4.13 | ||
| Contact: fabrice.gasnier@st.com | ||
| Description: | ||
| Reading returns the list possible active edges. | ||
|
|
||
| What: /sys/bus/iio/devices/iio:deviceX/in_count0_polarity | ||
| KernelVersion: 4.13 | ||
| Contact: fabrice.gasnier@st.com | ||
| Description: | ||
| Configure the device encoder/counter active edge: | ||
| - rising-edge | ||
| - falling-edge | ||
| - both-edges | ||
|
|
||
| In non-quadrature mode, device counts up on active edge. | ||
| In quadrature mode, encoder counting scenarios are as follows: | ||
| ---------------------------------------------------------------- | ||
| | Active | Level on | IN1 signal | IN2 signal | | ||
| | edge | opposite |------------------------------------------ | ||
| | | signal | Rising | Falling | Rising | Falling | | ||
| ---------------------------------------------------------------- | ||
| | Rising | High -> | Down | - | Up | - | | ||
| | edge | Low -> | Up | - | Down | - | | ||
| ---------------------------------------------------------------- | ||
| | Falling | High -> | - | Up | - | Down | | ||
| | edge | Low -> | - | Down | - | Up | | ||
| ---------------------------------------------------------------- | ||
| | Both | High -> | Down | Up | Up | Down | | ||
| | edges | Low -> | Up | Down | Down | Up | | ||
| ---------------------------------------------------------------- |
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27 changes: 27 additions & 0 deletions
27
Documentation/devicetree/bindings/iio/counter/stm32-lptimer-cnt.txt
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| STMicroelectronics STM32 Low-Power Timer quadrature encoder and counter | ||
|
|
||
| STM32 Low-Power Timer provides several counter modes. It can be used as: | ||
| - quadrature encoder to detect angular position and direction of rotary | ||
| elements, from IN1 and IN2 input signals. | ||
| - simple counter from IN1 input signal. | ||
|
|
||
| Must be a sub-node of an STM32 Low-Power Timer device tree node. | ||
| See ../mfd/stm32-lptimer.txt for details about the parent node. | ||
|
|
||
| Required properties: | ||
| - compatible: Must be "st,stm32-lptimer-counter". | ||
| - pinctrl-names: Set to "default". | ||
| - pinctrl-0: List of phandles pointing to pin configuration nodes, | ||
| to set IN1/IN2 pins in mode of operation for Low-Power | ||
| Timer input on external pin. | ||
|
|
||
| Example: | ||
| timer@40002400 { | ||
| compatible = "st,stm32-lptimer"; | ||
| ... | ||
| counter { | ||
| compatible = "st,stm32-lptimer-counter"; | ||
| pinctrl-names = "default"; | ||
| pinctrl-0 = <&lptim1_in_pins>; | ||
| }; | ||
| }; |
23 changes: 23 additions & 0 deletions
23
Documentation/devicetree/bindings/iio/timer/stm32-lptimer-trigger.txt
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| STMicroelectronics STM32 Low-Power Timer Trigger | ||
|
|
||
| STM32 Low-Power Timer provides trigger source (LPTIM output) that can be used | ||
| by STM32 internal ADC and/or DAC. | ||
|
|
||
| Must be a sub-node of an STM32 Low-Power Timer device tree node. | ||
| See ../mfd/stm32-lptimer.txt for details about the parent node. | ||
|
|
||
| Required properties: | ||
| - compatible: Must be "st,stm32-lptimer-trigger". | ||
| - reg: Identify trigger hardware block. Must be 0, 1 or 2 | ||
| respectively for lptimer1, lptimer2 or lptimer3 | ||
| trigger output. | ||
|
|
||
| Example: | ||
| timer@40002400 { | ||
| compatible = "st,stm32-lptimer"; | ||
| ... | ||
| trigger@0 { | ||
| compatible = "st,stm32-lptimer-trigger"; | ||
| reg = <0>; | ||
| }; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,49 @@ | ||
| * ROHM BD9571MWV Power Management Integrated Circuit (PMIC) bindings | ||
|
|
||
| Required properties: | ||
| - compatible : Should be "rohm,bd9571mwv". | ||
| - reg : I2C slave address. | ||
| - interrupt-parent : Phandle to the parent interrupt controller. | ||
| - interrupts : The interrupt line the device is connected to. | ||
| - interrupt-controller : Marks the device node as an interrupt controller. | ||
| - #interrupt-cells : The number of cells to describe an IRQ, should be 2. | ||
| The first cell is the IRQ number. | ||
| The second cell is the flags, encoded as trigger | ||
| masks from ../interrupt-controller/interrupts.txt. | ||
| - gpio-controller : Marks the device node as a GPIO Controller. | ||
| - #gpio-cells : Should be two. The first cell is the pin number and | ||
| the second cell is used to specify flags. | ||
| See ../gpio/gpio.txt for more information. | ||
| - regulators: : List of child nodes that specify the regulator | ||
| initialization data. Child nodes must be named | ||
| after their hardware counterparts: | ||
| - vd09 | ||
| - vd18 | ||
| - vd25 | ||
| - vd33 | ||
| - dvfs | ||
| Each child node is defined using the standard | ||
| binding for regulators. | ||
|
|
||
| Example: | ||
|
|
||
| pmic: pmic@30 { | ||
| compatible = "rohm,bd9571mwv"; | ||
| reg = <0x30>; | ||
| interrupt-parent = <&gpio2>; | ||
| interrupts = <0 IRQ_TYPE_LEVEL_LOW>; | ||
| interrupt-controller; | ||
| #interrupt-cells = <2>; | ||
| gpio-controller; | ||
| #gpio-cells = <2>; | ||
|
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||
| regulators { | ||
| dvfs: dvfs { | ||
| regulator-name = "dvfs"; | ||
| regulator-min-microvolt = <750000>; | ||
| regulator-max-microvolt = <1030000>; | ||
| regulator-boot-on; | ||
| regulator-always-on; | ||
| }; | ||
| }; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| * Device tree bindings for Nokia Retu and Tahvo multi-function device | ||
|
|
||
| Retu and Tahvo are a multi-function devices found on Nokia Internet | ||
| Tablets (770, N800 and N810). The Retu chip provides watchdog timer | ||
| and power button control functionalities while Tahvo chip provides | ||
| USB transceiver functionality. | ||
|
|
||
| Required properties: | ||
| - compatible: "nokia,retu" or "nokia,tahvo" | ||
| - reg: Specifies the CBUS slave address of the ASIC chip | ||
| - interrupts: The interrupt line the device is connected to | ||
| - interrupt-parent: The parent interrupt controller | ||
|
|
||
| Example: | ||
|
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||
| cbus0 { | ||
| compatible = "i2c-cbus-gpio"; | ||
| ... | ||
| retu: retu@1 { | ||
| compatible = "nokia,retu"; | ||
| interrupt-parent = <&gpio4>; | ||
| interrupts = <12 IRQ_TYPE_EDGE_RISING>; | ||
| reg = <0x1>; | ||
| }; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,48 @@ | ||
| STMicroelectronics STM32 Low-Power Timer | ||
|
|
||
| The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several | ||
| functions: | ||
| - PWM output (with programmable prescaler, configurable polarity) | ||
| - Quadrature encoder, counter | ||
| - Trigger source for STM32 ADC/DAC (LPTIM_OUT) | ||
|
|
||
| Required properties: | ||
| - compatible: Must be "st,stm32-lptimer". | ||
| - reg: Offset and length of the device's register set. | ||
| - clocks: Phandle to the clock used by the LP Timer module. | ||
| - clock-names: Must be "mux". | ||
| - #address-cells: Should be '<1>'. | ||
| - #size-cells: Should be '<0>'. | ||
|
|
||
| Optional subnodes: | ||
| - pwm: See ../pwm/pwm-stm32-lp.txt | ||
| - counter: See ../iio/timer/stm32-lptimer-cnt.txt | ||
| - trigger: See ../iio/timer/stm32-lptimer-trigger.txt | ||
|
|
||
| Example: | ||
|
|
||
| timer@40002400 { | ||
| compatible = "st,stm32-lptimer"; | ||
| reg = <0x40002400 0x400>; | ||
| clocks = <&timer_clk>; | ||
| clock-names = "mux"; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
|
|
||
| pwm { | ||
| compatible = "st,stm32-pwm-lp"; | ||
| pinctrl-names = "default"; | ||
| pinctrl-0 = <&lppwm1_pins>; | ||
| }; | ||
|
|
||
| trigger@0 { | ||
| compatible = "st,stm32-lptimer-trigger"; | ||
| reg = <0>; | ||
| }; | ||
|
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||
| counter { | ||
| compatible = "st,stm32-lptimer-counter"; | ||
| pinctrl-names = "default"; | ||
| pinctrl-0 = <&lptim1_in_pins>; | ||
| }; | ||
| }; |
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