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Log file reporting test failures on pins that were never tested #3

@timothyscherer

Description

@timothyscherer

None of these were tested, but some are behaving like they were.

------------------J10-------------------
   LVDS[4,4]	 Fail         expected LVDS, got RS422	0.0999			U202| 1   2   3     U203| 5   6   7     |9p->1p    5n->6n    
   LVDS[10,10]	 Fail         expected LVDS, got LVDS	0.1001			U204| 9   10  11    U205| 11  10  9     |8p->2p    4n->7n    

------------------J11-------------------
   LVDS[5,5]	 Fail         No test			U202| 7   6   5     U203| 3   2   1     |9p->1p    5n->6n    
   LVDS[11,11]	 Fail         No test			U204| 15  14  13    U205| 13  14  15    |8p->2p    4n->7n    

------------------J12-------------------
   xTTL[0,0]	 Fail         No test			U500| 3   4     U400| 3   4     |15->13    
   xTTL[1,1]	 Fail         No test			U500| 6   5     U400| 6   5     |14->9     
   xTTL[2,2]	 Fail         No test			U500| 10  11    U400| 10  11    |2->10     
   xTTL[3,3]	 Fail         No test			U500| 14  13    U400| 14  13    |1->12     
   xTTL[4,4]	 Fail         No test			U502| 10  11    U401| 3   4     |17->5     
   xTTL[5,5]	 Fail         No test			U502| 14  13    U401| 6   5     |16->1     
   xTTL[6,6]	 Fail         No test			U502| 3   4     U401| 10  11    |4->2      
   xTTL[7,7]	 Fail         No test			U502| 6   5     U401| 14  13    |3->4      
   xTTL[0,8]	 Fail         No test			U504| 10  11    U400| 3   4     |6->13     
   xTTL[1,9]	 Fail         No test			U504| 14  13    U400| 6   5     |19->9     
   xTTL[2,10]	 Fail         No test			U504| 3   4     U400| 10  11    |7->10     
   xTTL[3,11]	 Fail         No test			U504| 6   5     U400| 14  13    |18->12    
   xTTL[4,12]	 Fail         No test			U506| 10  11    U401| 3   4     |13->5     
   xTTL[5,13]	 Fail         No test			U506| 14  13    U401| 6   5     |25->1     
   xTTL[6,14]	 Fail         No test			U506| 3   4     U401| 10  11    |12->2     
   xTTL[7,15]	 Fail         No test			U506| 6   5     U401| 14  13    |24->4     
   xTTL[0,16]	 Fail         expected TTL, got TTL	1.0000			U508| 10  11    U400| 3   4     |8->13     
   xTTL[1,17]	 Fail         expected TTL, got TTL	1.0000			U508| 14  13    U400| 6   5     |21->9     
   xTTL[2,18]	 Fail         No test			U508| 3   4     U400| 10  11    |22->10    
   xTTL[3,19]	 Fail         No test			U508| 6   5     U400| 14  13    |9->12     

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